xcv100-5tqg144i Xilinx Corp., xcv100-5tqg144i Datasheet - Page 20

• Manufacturer Part Number: xcv100-5tqg144i
• Manufacturer: Xilinx Corp.

Virtex™ 2.5 V Field Programmable Gate Arrays
3. At the rising edge of CCLK: If BUSY is Low, the data is
4. Repeat steps 2 and 3 until all the data has been sent.
Module 2 of 4
16
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this has happened.
DATA[0:7]
WRITE
CCLK
BUSY
CS
5
3
1
Write
Figure 16: Write Operations
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Write
2
5. De-assert CS and WRITE.
A flowchart for the write operation appears in
Note that if CCLK is slower than f
asserts BUSY. In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
No Write
7
Write
4
6
ds003_16_071902
DS003-2 (v2.8.1) December 9, 2002
CCNH
Product Specification
, the FPGA never
Figure
17.
R