epf10k100ef484 Altera Corporation, epf10k100ef484 Datasheet - Page 34

• Manufacturer Part Number: epf10k100ef484
• Description: Embedded Programmable Logic Device
• Manufacturer: Altera Corporation

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
34
Table 9. Peripheral Bus Sources for EPF10K100E, EPF10K130E, EPF10K200E & EPF10K200S Devices
OE0
OE1
OE2
OE3
OE4
OE5
CLKENA0/CLK0/GLOBAL0
CLKENA1/OE6/GLOBAL1
CLKENA2/CLR0
CLKENA3/OE7/GLOBAL2
CLKENA4/CLR1
CLKENA5/CLK1/GLOBAL3
Control Signal
Peripheral
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3 in
generated signal can drive a global signal, providing the same low-skew,
low-delay characteristics as a signal driven by an input pin. An LE drives
the global signal by driving a row line that drives the peripheral bus,
which then drives the global signal. This feature is ideal for internally
generated clear or clock signals with high fan-out. However, internally
driven global signals offer no advantage over the general-purpose
interconnect for routing data signals. The dedicated input pin should be
driven to a known logic state (such as ground) and not be allowed to float.
The chip-wide output enable pin is an active-high pin (DEV_OE) that can
be used to tri-state all pins on the device. This option can be set in the
Altera software. On EPF10K50E and EPF10K200E devices, the built-in I/O
pin pull-up resistors (which are active during configuration) are active
when the chip-wide output enable pin is asserted. The registers in the IOE
can also be reset by the chip-wide reset pin.
EPF10K100E
Row A
Row C
Row E
Row L
Row I
Row K
Row F
Row D
Row B
Row H
Row J
Row G
EPF10K130E
Row C
Row E
Row G
Row N
Row K
Row M
Row H
Row F
Row D
Row J
Row L
Row I
Tables 8
and 9. An internally
Altera Corporation
EPF10K200S
EPF10K200E
Row G
Row I
Row K
Row R
Row O
Row Q
Row L
Row J
Row H
Row N
Row P
Row M