ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 79

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ep1c6t144i8es

Manufacturer Part Number
ep1c6t144i8es
Description
Cyclone Fpga Family
Manufacturer
Altera Corporation
Datasheet
Preliminary Information
Altera Corporation
External Timing Parameters
External timing parameters are specified by device density and speed
grade.
All registers are within the IOE.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
M4KRC
M4KWC
M4KWERESU
M4KWEREH
M4KBESU
M4KBEH
M4KDATAASU
M4KDATAAH
M4KADDRASU
M4KADDRAH
M4KDATABSU
M4KDATABH
M4KADDRBSU
M4KADDRBH
M4KDATACO1
M4KDATACO2
M4KCLKHL
M4KCLR
R4
C4
LOCAL
Table 47. M4K Block Internal Timing Microparameters
Table 48. Routing Delay Internal Timing Microparameters
Symbol
Symbol
Figure 38
shows the timing model for bidirectional IOE pin timing.
Min
Min
105
286
72
43
72
43
72
43
72
43
72
43
72
43
-6
-6
4,379
2,910
4,351
Max
Max
621
261
338
244
Min
Min
120
328
82
49
82
49
82
49
82
49
82
49
82
49
Cyclone FPGA Family Data Sheet
-7
-7
5,035
3,346
5,003
Max
Max
714
300
388
281
Min
Min
136
371
93
55
93
55
93
55
93
55
93
55
93
55
-8
-8
5,691
3,783
5,656
Max
Max
807
339
439
318
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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