dsp56371 Freescale Semiconductor, Inc, dsp56371 Datasheet - Page 47

• Manufacturer Part Number: dsp56371
• Description: Dsp56371 Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

13.1 Programming the Serial Clock
The programmed serial clock cycle, T
HCKR (SHI clock control register).
The expression for T
Freescale Semiconductor
Note:
No.
52
53
54
55
56
57
58
59
60
61
where
— HRS is the pre-scaler rate select bit. When HRS is cleared, the fixed
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00
1. VCORE_VDD = 1.2 5 ± 0.05 V; T
2. Pull-up resistor: R
3. Capacitive load: C
4. All times assume noise free inputs
5. All times assume internal clock frequency of 180MHz
Data set-up time
Data hold time
DSP clock frequency
SCL low to data out valid
Stop condition setup time
HREQ in deassertion to last SCL edge (HREQ in
set-up time)
First SCL sampling edge to HREQ output
deassertion
Last SCL edge to HREQ output not deasserted
HREQ in assertion to first SCL edge
First SCL edge to HREQ in not asserted
(HREQ in hold time.)
divide-by-eight pre-scaler is operational. When HRS is set, the pre-scaler is bypassed.
to $FF) may be selected.
I
2
CCP
Characteristics
T
P
I
b
2
(min) = 1.5 kOhm
(max) = 50 pF
CCP
is
= [T
Table 21. SHI I
C
J
× 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
1
= –40°C to 115°C for 150 MHz; T
I
2
CCP
DSP56371 Data Sheet, Rev. 4.1
, is specified by the value of the HDM[7:0] and HRS bits of the
2
C Protocol Timing (continued)
Standard I
-0.5
0.5
Expression
4
2
Symbol/
T
T
×
T
×
T
T
T
T
t
t
NG;RQO
SU;RQI
AS;RQO
HO;RQI
2
HD;DAT
F
SU;STO
×
SU;DAT
VD;DAT
AS;RQI
×
T
T
C*
OSC
C
C
T
T
I
C
2
+ 30
+ 30
CCP
- 21
J
= 0°C to 100°C for 181 MHz; CL = 50 pF
Serial Host Interface (SHI) I
4327
10.6
Min
250
0.0
4.0
0.0
0.0
52
—
—
Standard
Max
3.4
52
—
—
—
—
—
—
—
—
28.5
Min
100
927
0.0
0.6
0.0
0.0
52
—
—
Fast-Mode
2
C Protocol Timing
Max
0.9
0.9
52
—
—
—
—
—
—
—
MHz
Unit
ns
µs
µs
µs
ns
ns
ns
ns
ns
Eqn. 1
47