adsp-21462w Analog Devices, Inc., adsp-21462w Datasheet - Page 32

• Manufacturer Part Number: adsp-21462w
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21462W/ADSP-21465W/ADSP-21467
Memory Read
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 26. Memory Read
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x t
IC = (number of idle cycles specified in AMICTLx register) x t
H = (number of hold cycles specified in AMICTLx register) x t
Data delay/setup: System must meet t
The falling edge of AMI_MSx, is referenced.
Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.
Data hold: User must meet t
AMI_ACK delay/setup: User must meet t
DAD
DRLD
SDS
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
ADDRESS
MSx
DATA
ACK
WR
RD
—
Address, Selects Delay to Data Valid
AMI_RD Low to Data Valid
Data Setup to AMI_RD High
Data Hold from AMI_RD High
AMI_ACK Delay from Address, Selects
AMI_ACK Delay from AMI_RD Low
Address Selects Hold After AMI_RD High
Address Selects to AMI_RD Low
AMI_RD Pulse Width
AMI_RD High to AMI_WR, AMI_RD, Low
Bus Master
HDRH
—
Bus Master
in asynchronous access mode. See
DAD
t
DARL
t
DAAK
, t
DAAK
DRLD
, or t
, or t
DSAK
SDS.
1
, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet t
t
t
DSAK
DAD
3, 4
2
Rev. PrA | Page 32 of 60 | November 2008
Figure 18. Memory Read—Bus Master
4
1, 2
t
DRLD
2, 5
Test Conditions on Page 53
DDR2_CLK
DDR2_CLK
DDR2_CLK
t
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
RW
).
.
.
for the calculation of hold times given capacitive and dc loads.
t
SDS
DDR2_CLK
Preliminary Technical Data
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
t
DRHA
HDRH
t
RWR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DAAK
or t
DSAK
.