epm3064a Altera Corporation, epm3064a Datasheet - Page 37

• Manufacturer Part Number: epm3064a
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
t
t
t
t
t
t
f
t
f
t
t
t
t
t
t
t
t
t
t
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 24. EPM3512A External Timing Parameters
Table 25. EPM3512A Internal Timing Parameters (Part 1 of 2)
Symbol
Symbol
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay,
slow slew rate = off
V
Output buffer and pad delay,
slow slew rate = off
V
CCIO
CCIO
= 3.3 V
= 2.5 V
Parameter
Parameter
(2)
C1 = 35 pF
(3)
(2)
(2),
(2)
(2),
C1 = 35 pF
C1 = 35 pF
Conditions
Conditions
MAX 3000A Programmable Logic Device Family Data Sheet
(4)
(4)
Note (1)
(2)
116.3
116.3
Min
Min
3.0
3.0
0.2
1.0
3.0
-7
-7
Note (1)
Max
Max
Speed Grade
7.8
8.6
8.6
Speed Grade
0.7
0.7
3.1
2.7
0.4
2.2
1.0
0.0
1.0
1.5
87.0
87.0
Min
Min
0.3
1.0
4.0
4.0
4.0
-10
-10
Max
10.4
11.5
11.5
Max
0.9
0.9
3.6
3.5
0.5
2.8
1.3
0.0
1.5
2.0
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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