ad1939xstzrl Analog Devices, Inc., ad1939xstzrl Datasheet

ad1939xstzrl

Manufacturer Part Number

ad1939xstzrl

Description

4 Adc/8 Dac With Pll, 192 Khz, 24 Bit Codec

Manufacturer

Analog Devices, Inc.

Datasheet

1.AD1939XSTZRL.pdf (30 pages)

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Preliminary Technical Data

Features

PLL generated (32-192kHz) or direct master clock

Low EMI design

109 dB DAC/ 107dB ADC Dynamic Range and SNR

-94dB THD+N

Single 3.3V Supply

Tolerance for 5V logic inputs

Supports 24-bits and 8 kHz - 192 kHz sample rates

Differential ADC input

Single-ended or Differential DAC output versions

Log volume control with "auto-ramp" function

Hardware and software controllable clickless mute

Software and hardware power-down

Right justified, left justified, I

Master and slave modes up to 16 channel in/out

48-lead LQFP or 64-lead LQFP plastic package

Functional Block Diagram

Rev. PrI

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

S and TDM Modes

Analog

Inputs

Audio

ADC

Reference

AD193X

Precision

Voltage

Digital

Filter

SDATAOUT

AD1935/AD1936/AD1937/AD1938/AD1939

Timing Management

Serial Data Port

(Clock & PLL)

Digital Audio

Input/Output

Control Data

Input/Output

Control Port

Control

Figure 1

SPI / I

CLOCKS

SDATAIN

Applications

Automotive audio systems

Home theater systems

Set-top boxes

Digital audio effects processors

GENERAL DESCRIPTION

The AD193X family are high performance, single-chip codecs that

provide 4 ADCs with differential input and 8 DACs with either

single-ended or differential output using ADI’s patented multibit

sigma-delta architecture. An SPI® or I

a microcontroller to adjust volume and many other parameters.

The AD193X family operates from 3.3V digital and analog supplies.

The AD193X is available in a 48-lead (SE output) or 64-lead

(differential output) LQFP package.

The AD193X is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures. By

using the on-board PLL to derive master clock from L-R clock, the

AD193X eliminates the need for a separate high frequency master

clock. It can also be used with a suppressed bit clock. The D-A and

A-D converters are designed using the latest ADI continuous time

architectures to further minimize EMI. By using 3.3V supplies,

power consumption is minimized, further reducing emissions.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

Volume

Control

Digital

Filter

DAC

192 kHz, 24 Bit CODEC

4 ADC/8 DAC with PLL,

Outputs

Analog

Audio

C® port is included, allowing

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ad1939xstzrl Summary of contents

Page 1

... ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC 2 C® port is included, allowing DAC DAC DAC DAC DAC DAC Analog Analog DAC DAC Audio Audio Outputs Outputs DAC DAC DAC DAC DAC DAC DAC DAC www.analog.com © 2005 Analog Devices, Inc. All rights reserved. ...

Page 2

AD1935/AD1936/AD1937/AD1938/AD1939 AD193X—SPECIFICATIONS Test Conditions, Unless Otherwise Noted. Performance of all channels is identical (exclusive of the Inter-channel Gain Mismatch and Inter-channel Phase Deviation specifications). Parameter Supply Voltages (AVDD, DVDD) Case Temperature Master Clock Input Signal Input Sample Rate Measurement Bandwidth ...

Page 3

Preliminary Technical Data Parameter REFERENCE Crystal Oscillator Parameter Transconductance Digital I/O Parameter Input Voltage Input Voltage Input Leakage ( 2 Input Leakage ( ...

Page 4

AD1935/AD1936/AD1937/AD1938/AD1939 Temperature Range Parameter Specifications Guaranteed Functionality Guaranteed Storage Digital Filters Mode ADC All Modes, DECIMATION Typ @ 48 kHz FILTER 48 kHz Mode, Typ @ 48 kHz DAC 96 kHz Mode, INTERPOLATION Typ @ 96 kHz FILTER 192 kHz ...

Page 5

Preliminary Technical Data Parameter PORT Start Condition Stop Condition t t Slave Mode f t DAC SERIAL PORT t Master Mode Slave ...

Page 6

AD1935/AD1936/AD1937/AD1938/AD1939 ABSOLUTE MAXIMUM RATINGS Parameter Min Analog (AVDD) –0.3 Digital (DVDD) –0.3 Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) –0.3 Digital Input Voltage (Signal Pins) –0.3 Case Temperature (Operating) –40 Table 9 Stresses above those listed under ...

Page 7

Preliminary Technical Data Figure 2. ADC Passband Filter Response, 48 kHz Figure 4. DAC Passband Filter Response, 48 kHz Figure 6. DAC Passband Filter Response, 96 kHz AD1935/AD1936/AD1937/AD1938/AD1939 Figure 3. ADC Stopband Filter Response, 48 kHz Figure 5. DAC Stopband ...

Page 8

AD1935/AD1936/AD1937/AD1938/AD1939 Figure 8. DAC Passband Filter Response, 192 kHz Preliminary Technical Data Figure 9. DAC Stopband Filter Response, 192 kHz Rev. PrI | Page ...

Page 9

Preliminary Technical Data FUNCTIONAL OVERVIEW ADCs There are four ADC channels in the AD193X configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 192 kHz. The ADCs ...

Page 10

AD1935/AD1936/AD1937/AD1938/AD1939 oscillator generate the master clock. In addition especially important that the clock signal should not be passed through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD193X. In ...

Page 11

Preliminary Technical Data SCK 0 SDA 0 0 START BY MASTER CHIP ADDRESS BYTE SCL SDA START BY MASTER CHIP ADDRESS BYTE SCL (Continued) SDA (Continued) REPEATED START BY MASTER CHIP ADDRESS BYTE Power ...

Page 12

AD1935/AD1936/AD1937/AD1938/AD1939 Serial Data Ports—Data Format The eight DAC channels output or accept a common serial bit clock and left-right framing clock to clock in the serial data. The four ADC channels output or accept a common serial bit clock and ...

Page 13

Preliminary Technical Data t DBH DBCLK t DBL t DLS DLRCLK t DDS DSDATA LEFT-JUSTIFIED MSB MODE t DDH DSDATA 2 I S-JUSTIFIED MODE DSDATA RIGHT-JUSTIFIED MODE t ABH ABCLK t ABL t ALS ALRCLK t ABDD ASDATA LEFT-JUSTIFIED MODE ...

Page 14

AD1935/AD1936/AD1937/AD1938/AD1939 LRCLK LRCLK BCLK BCLK DATA DATA LRCLK LRCLK BCLK BCLK DATA DATA FSTDM BCLK TDM MSB TDM ASDATA1 1ST CH TDM (OUT) ADC L1 ASDATA 32 MSB TDM DSDATA1 1ST CH TDM (IN) DSDATA1 DAC L1 32 AUX LRCLK ...

Page 15

Preliminary Technical Data Pin Function Changes in TDM and AUX Modes Pin Name Stereo Modes ASDATA1 ADC1 Data Out ASDATA2 ADC2 Data Out DSDATA1 DAC1 Data In DSDATA2 DAC2 Data In DSDATA3 DAC3 Data In DSDATA4 DAC4 Data In ALRCLK ...

Page 16

AD1935/AD1936/AD1937/AD1938/AD1939 PIN FUNCTION DESCRIPTIONS 48-Lead LQFP Plastic Package – AD1936, AD1938 Pin No. In/Out Mnemonic Description 1 I AGND Analog Ground MCLKI/XI Master Clock Input/ Crystal Oscillator Input MCLK/XO Master Clock Output/ Crystal Oscillator Output. 4 ...

Page 17

Preliminary Technical Data 64-Lead LQFP Plastic Package – AD1937, AD1939 Pin No. In/Out Mnemonic Description 1 I AGND Analog Ground MCLKI/XI Master Clock Input/ Crystal Oscillator Input MCLK/XO Master Clock Output/ Crystal Oscillator Output ...

Page 18

AD1935/AD1936/AD1937/AD1938/AD1939 Pin No. In/Out Mnemonic Description Common Mode Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND ADC1LP ADC1 Left Positive Input ADC1LN ADC1 Left Negative Input ADC1RP ADC1 ...

Page 19

Preliminary Technical Data Pin No. In/Out Mnemonic Description 36 O OL1 DAC 1 Left Output Connect OR1 DAC 1 Right Output Connect OL2 DAC 2 Left Output ...

Page 20

AD1935/AD1936/AD1937/AD1938/AD1939 AGND MCLKI/XI MCLKO/XO AGND AVDD OR3P OR3N OR4P OR4N PD/RST DSDATA4 DGND AGND MCLKI/XI MCLKO/XO AGND AVDD PD/RST DSDATA4 DGND OL3P ...

Page 21

Preliminary Technical Data APPLICATION CIRCUITS Figure 24. Typical DAC Output Filter Circuit (Single-ended, Non-inverting) AD1935/AD1936/AD1937/AD1938/AD1939 Figure 23. Typical ADC Input Filter Circuit Figure 25. Typical DAC Output Filter Circuit (Single-ended, Inverting) Figure 26. Typical DAC Output Filter Circuit (Differential) Rev. ...

Page 22

AD1935/AD1936/AD1937/AD1938/AD1939 Figure 27. Recommended Loop Filters for LRCLK or MCLK PLL reference. Figure 28. Recommended 3.3V Regulator Circuit (64-lead versions) Rev. PrI | Page Preliminary Technical Data ...

Page 23

Preliminary Technical Data REGISTER DEFINITIONS Register format Global Address R/W Bit 23: Note 1: The format is the same for I C and SPI. Note 2: Global address for the AD193X series is 0x04, shifted left 1 bit ...

Page 24

AD1935/AD1936/AD1937/AD1938/AD1939 PLL AND CLOCK CONTROL REGISTERS PLL and Clock control 0 Bit Value Function 0 0 Normal operation 1 Power down 2:1 00 INPUT 256 (x 44.1 or 48kHz) 01 INPUT 384 (x 44.1 or 48kHz) 10 INPUT 512 (x ...

Page 25

Preliminary Technical Data DAC CONTROL REGISTERS DAC control 0 Bit Value Function 0 0 Normal 1 Power down 2:1 00 32/44.1/48 kHz 01 64/88.2/96 kHz 10 128/176.4/192 kHz 11 Reserved 5:3 000 1 001 0 010 8 011 12 100 ...

Page 26

AD1935/AD1936/AD1937/AD1938/AD1939 DAC control 2 Bit Value Function 0 0 Unmute 1 Mute 2:1 00 Flat 01 48 kHz Curve 10 44.1 kHz Curve 11 32 kHz Curve 4 Reserved Non-inverted 1 ...

Page 27

Preliminary Technical Data ADC CONTROL REGISTERS ADC control 0 Bit Value Function 0 0 Normal 1 Power down 1 0 Off Unmute 1 Mute 3 0 Unmute 1 Mute 4 0 Unmute 1 Mute 5 0 ...

Page 28

AD1935/AD1936/AD1937/AD1938/AD1939 ADC control 2 Bit Value Function 0 0 50/50 (allows 32/24/20/16 BCLK/channel) 1 Pulse (32 BCLK/channel Drive out on falling edge (DEF) 1 Drive out on rising edge 2 0 Left Low 1 Left High 3 0 ...

Page 29

Preliminary Technical Data OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 0.05 VIEW A ROTATED 90° CCW ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can ...

Page 30

... AD1937XSTZRL –40°C to +105°C AD1938XSTZ –40°C to +105°C AD1938XSTZRL –40°C to +105°C AD1939XSTZ –40°C to +105°C AD1939XSTZRL –40°C to +105°C EVAL-AD1935EB EVAL-AD1936EB EVAL-AD1937EB EVAL-AD1938EB EVAL-AD1939EB Note: All parts are lead-free © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies ...

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