pca9555bs NXP Semiconductors, pca9555bs Datasheet
pca9555bs
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pca9555bs Summary of contents
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... The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I enhance the NXP Semiconductors family of I include higher drive capability I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9555 consists of two 8-bit Confi ...
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... PCA9555D PCA9555DB PCA9555PW TSSOP24 PCA9555BS PCA9555HF 3.1 Ordering options Table 2. Type number PCA9555N PCA9555D PCA9555DB PCA9555PW PCA9555BS PCA9555HF PCA9555_7 Product data sheet 16-bit I Ordering information Name Description DIP24 plastic dual in-line package; 24 leads (600 mil) SO24 plastic small outline package; 24 leads; body width 7.5 mm SSOP24 plastic shrink small outline package ...
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... NXP Semiconductors 4. Block diagram SCL SDA Fig 1. Block diagram of PCA9555 5. Pinning information 5.1 Pinning IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 Fig 2. Pin configuration for DIP24 PCA9555_7 Product data sheet 16-bit I PCA9555 2 I C-BUS/SMBus INPUT FILTER POWER-ON RESET Remark: All I/Os are set to inputs at reset ...
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... IO1_4 9 16 IO1_3 10 15 IO1_2 11 14 IO1_1 12 13 IO1_0 002aac699 IO1_7 3 16 IO1_6 PCA9555BS 4 15 IO1_5 5 14 IO1_4 6 13 IO1_3 002aac701 Transparent top view Rev. 07 — 5 June 2007 PCA9555 2 C-bus and SMBus I/O port with interrupt INT IO0_0 ...
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... NXP Semiconductors 5.2 Pin description Table 3. Symbol INT A1 A2 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 V SS IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 A0 SCL SDA V DD [1] HVQFN and HWQFN package die supply ground is connected to both the V pad. The V electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors 6. Functional description Refer to 6.1 Device address Fig 8. PCA9555 device address 6.2 Registers 6.2.1 Command byte The command byte is the first byte to follow the address byte during a write transmission used as a pointer to determine which of the following registers will be written or read. Table 4. Command ...
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... NXP Semiconductors 6.2.2 Registers 0 and 1: Input port registers This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. ...
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... NXP Semiconductors 6.2.5 Registers 6 and 7: Configuration registers This register configures the directions of the I/O pins bit in this register is set (written with ‘1’), the corresponding port pin is enabled as an input with high-impedance output driver bit in this register is cleared (written with ‘0’), the corresponding port pin is enabled as an output ...
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... NXP Semiconductors data from shift register data from shift register configuration write pulse read pulse data from shift register write polarity Fig 9. Simplified schematic of I/Os 6.5 Bus transactions 6.5.1 Writing to the port registers Data is transmitted to the PCA9555 by sending the device address and setting the least signifi ...
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SCL slave address SDA START condition R/W write to port data out from port 0 data out from port 1 Fig 10. Write ...
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... NXP Semiconductors 6.5.2 Reading the port registers In order to read data from the PCA9555, the bus master must first send the PCA9555 address with the least significant bit set to a logic 0 (see address”). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least signifi ...
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SCL slave address I0.x SDA START condition R/W acknowledge from slave read from port 0 data into ...
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SCL R/W slave address I0.x SDA DATA 00 START condition acknowledge from slave t h(D) read from port 0 data into ...
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... NXP Semiconductors 6.5.3 Interrupt output The open-drain interrupt output is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read (see output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around ...
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... NXP Semiconductors 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL MASTER ...
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... NXP Semiconductors 8. Application design-in information MASTER CONTROLLER SCL SDA INT GND Device address configured as 0100 000xb for this example. IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs. ...
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... NXP Semiconductors 9. Limiting values Table 13. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol I tot T stg T amb PCA9555_7 Product data sheet 16-bit I Limiting values Parameter supply voltage voltage on an input/output pin output current ...
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... NXP Semiconductors 10. Static characteristics Table 14. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...
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... NXP Semiconductors [2] Each I/O must be externally limited to a maximum and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. [3] The total current sourced by all I/Os must be limited to 160 mA. 6 (V) 5.0 4.0 (1) 3.0 (2) 2.0 2.7 3.6 ( ...
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... NXP Semiconductors 11. Dynamic characteristics Table 15. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t set-up time for a repeated START SU;STA condition t set-up time for STOP condition SU;STO ...
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... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 23. Definition of timing on the I 12. Test information Fig 24. Test circuitry for switching times Fig 25. Load circuit PCA9555_7 Product data sheet 16-bit HD;DAT HIGH SU;DAT 2 C-bus V I PULSE GENERATOR R = load resistor ...
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... NXP Semiconductors 13. Package outline DIP24: plastic dual in-line package; 24 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 5.1 0.51 4 inches 0.2 0.02 0.16 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 28 ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 0.75 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0.30 mm 0.8 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 15. Soldering 15.1 Introduction There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fi ...
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... NXP Semiconductors packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16 Table 16. Package thickness (mm) < 2.5 2.5 Table 17. Package thickness (mm) < 1.6 1.6 to 2.5 > 2.5 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during refl ...
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... NXP Semiconductors 15.3.2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • ...
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... NXP Semiconductors Table 18. Suitability of IC packages for wave, reflow and dipping soldering methods Mounting Package Surface mount BGA, HTSSON..T LFBGA, SQFP, SSOP..T VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS [7] PLCC LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN ...
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... NXP Semiconductors 16. Abbreviations Table 19. Acronym CMOS GPIO 2 I C-bus SMBus I/O ACPI LED ESD HBM MM CDM PCB FET MSB LSB PCA9555_7 Product data sheet 16-bit I Abbreviations Description Complementary Metal Oxide Semiconductor General Purpose Input/Output Inter-Integrated Circuit bus System Management Bus Input/Output Advanced Configuration and Power Interface ...
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... Release date PCA9555_7 20070605 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • added HWQFN24 (SOT994-1) package option • ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Registers 6.2.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.2 Registers 0 and 1: Input port registers . . . . . . . 7 6.2.3 Registers 2 and 3: Output port registers 6.2.4 Registers 4 and 5: Polarity Inversion registers . 7 6.2.5 Registers 6 and 7: Confi ...