hi7191 Intersil Corporation, hi7191 Datasheet - Page 16

• Manufacturer Part Number: hi7191
• Description: 24-bit, High Precision, Sigma Delta A/d Converter
• Manufacturer: Intersil Corporation

Normal operation in self-clocking mode is as follows (See
Figure 12): CS is sampled low on falling OSC
SCLK transition output is delayed 29 OSC
next rising OSC
high for 28 OSC
SCLK will again transition eight times and stall high. This
sequence will repeat continuously while CS is active.
The extra OSC
inactive state is a one clock cycle latency required to
properly sample the CS input. Note that the normal stall at
byte boundaries is 28 OSC
to rising edge stall period of 32 OSC
The effects of CS on the I/O are different for self-clocking
mode (MODE = 1) than for external mode (MODE = 0). For
external clocking mode CS inactive disables the I/O state
machine, effectively freezing the state of the I/O cycle. That
is, an I/O cycle can be interrupted using chip select and the
HI7191 will continue with that I/O cycle when re-enabled via
CS. SCLK can continue toggling while CS is inactive. If CS
goes inactive during an I/O cycle, it is up to the user to
ensure that the state of SCLK is identical when reactivating
CS as to what it was when CS went inactive. For read
operations in external clocking mode, the output will go
three-state immediately upon deactivation of CS.
For self-clocking mode (MODE = 1), the effects of CS are
different. If CS transitions high (inactive) during the period when
data is being transferred (any non stall time) the HI7191 will
complete the data transfer to the byte boundary. That is, once
SCLK begins the eight transition sequence, it will always
complete the eight cycles. If CS remains inactive after the byte
has been transferred it will be sampled and SCLK will remain
stalled high indefinitely. If CS has returned to active low before
the data byte transfer period is completed the HI7191 acts as if
CS was active during the entire transfer period.
It is important to realize that the user can interrupt a data
transfer on byte boundaries. That is, if the Instruction
Register calls for a 3 byte transfer and CS is inactive after
only one byte has been transferred, the HI7191, when
reactivated, will continue with the remaining two bytes before
looking for the next Instruction Register write cycle.
Note that the outputs will NOT go three-state immediately upon
CS inactive for read operations in self-clocking mode. In the
case of CS going inactive during a read cycle the outputs
remain driving until after the last data bit is transferred. In the
case of CS inactive during the clock stall time it takes 1 OSC
cycle plus prop delay (Max) for the outputs to be disabled.
I/O Port Pin Descriptions
The serial I/O port is a bidirectional port which is used to
read the data register and read or write the control register
and calibration registers. The port contains two data lines, a
synchronous clock, and a status flag. Figure 11 shows a
diagram of the serial interface lines.
1
1
1
. SCLK transitions eight times and then stalls
cycle required when coming out of the CS
cycles. After this stall period is completed
1
cycles thus giving a SCLK rising
16
1
cycles.
1
cycles from the
1
edges. The first
1
HI7191
SDO - Serial Data out. Data is read from this line using those
protocols with separate lines for transmitting and receiving
data. An example of such a standard is the Motorola Serial
Peripheral Interface (SPI) using the 68HC05 and 68HC11
family of microcontrollers, or other similar processors. In the
case of using bidirectional data transfer on SDIO, SDO does
not output data and is set in a high impedance state.
SDIO - Serial Data in or out. Data is always written to the
device on this line. However, this line can be used as a
bidirectional data line. This is done by properly setting up the
Control Register. Bidirectional data transfer on this line can
be used with Intel standard serial interfaces (SSR, Mode 0)
in MCS51 and MCS96 family of microcontrollers, or other
similar processors.
SCLK - Serial clock. The serial clock pin is used to
synchronize data to and from the HI7191 and to run the port
state machines. In Synchronous External Clock Mode, SCLK
is configured as an input, is supplied by the user, and can
run up to a 5MHz rate. In Synchronous Self Clocking Mode,
SCLK is configured as an output and runs at OSC
CS - Chip select. This signal is an active low input that
allows more than one device on the same serial
communication lines. The SDO and SDIO will go to a high
impedance state when this signal is high. If driven high
during any communication cycle, that cycle will be
suspended until CS reactivation. Chip select can be tied low
in systems that maintain control of SCLK.
DRDY - Data Ready. This is an output status flag from the
device to signal that the Data Output Register has been
updated with the new conversion result. DRDY is useful as an
edge or level sensitive interrupt signal to a microprocessor or
microcontroller. DRDY low indicates that new data is available
at the Data Output Register. DRDY will return high upon
completion of a complete Data Output Register read cycle.
MODE - Mode. This input is used to select between
Synchronous Self Clocking Mode (‘1’) or the Synchronous
External Clocking Mode (‘0’). When this pin is tied to V
serial port is configured in the Synchronous Self Clocking
mode where the synchronous shift clock (SCLK) for the serial
port is generated by the HI7191 and has a frequency of
OSC
configured for the Synchronous External Clocking Mode
where the synchronous shift clock for the serial port is
generated by an external device up to a maximum frequency
of 5MHz.
1
/8. When the pin is tied to DGND the serial port is
BIDIRECTIONAL DATA
FIGURE 11. HI7191 SERIAL INTERFACE
DEVICE STATUS
CLOCK MODE
CHIP SELECT
PORT CLOCK
DATA OUT
SDO
SDIO
SCLK
CS
DRDY
MODE
HI7191
1
/8.
June 1, 2006
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FN4138.8
the