tda8792m NXP Semiconductors, tda8792m Datasheet - Page 8

• Manufacturer Part Number: tda8792m
• Description: 3.3 V, 25 Mhz 8-bit Analog-to-digital Converter Adc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
2. The analog bandwidth is defined as the maximum full-scale input sine wave frequency which can be applied to the
3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
5. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
6. Output data acquisition: the output data is available after the maximum delay time of t
7. Maximum value standby mode start-up output delay time (HIGH-to-LOW transition):
1996 Feb 21
E
EB
D
G
D
Timing (f
t
t
t
3-state output delay times; see Fig.4
t
t
t
t
Standby mode output delay times
t
t
SYMBOL
ds
h
d
dZH
dZL
dHZ
dLZ
dSTBLH
dSTBHL
diff
FFECTIVE BITS
IFFERENTIAL GAIN
IFFERENTIAL PHASE
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
diff
must not be less than 1 ns.
device. No glitches greater than 8 LSBs are observed in the reconstructed signal neither is there any significant
attenuation.
input (square-wave signal) in order to sample the signal and obtain correct output data.
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
digital-to-analog converter.
operation, the hardware design must be taken into account the t
of the acquisition circuit.
clk
effective bits
differential gain
differential phase
sampling delay time
output hold time
output delay time
enable HIGH
enable LOW
disable HIGH
disable LOW
standby (LOW-to-HIGH transition)
start-up (HIGH-to-LOW transition)
= 25 MHz); see Fig.3 and note 6
; see Figs 6 and 11; note 4
; see note 5
; see note 5
PARAMETER
f
f
PAL modulated ramp
f
PAL modulated ramp
clk
clk
clk
f
f
f
f
i
i
i
i
= 25 MHz
= 25 MHz;
= 25 MHz;
= 2.0 MHz
= 4.43 MHz
= 7.5 MHz
= 10 MHz
8
CONDITIONS
d
and t
h
limits with respect to the input characteristics
6.02 + 1.76 dB.
6
8
MIN.
d
100
. In the event of 25 MHz clock
+
7.4
7.3
7.2
7.0
1.5
0.5
13
17
22
20
22
------------------------
f
clk
TYP.
7000
Product specification
(MHz)
TDA8792
2
25
28
30
28
30
200
note 7 ns
MAX.
.
bits
bits
bits
bits
%
deg
ns
ns
ns
ns
ns
ns
ns
ns
UNIT