adc11c170lfeb National Semiconductor Corporation, adc11c170lfeb Datasheet - Page 4

• Manufacturer Part Number: adc11c170lfeb
• Description: 11-bit, 170 Msps, 1.1 Ghz Bandwidth A/d Converter With Cmos Outputs
• Manufacturer: National Semiconductor Corporation

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DIGITAL I/O
ANALOG POWER
1, 6, 9, 37, 40,
DIGITAL POWER
2, 5, 10, 38,
39, 42, 47
15, 25, 36
16, 26, 35
Pin No.
20-24,
41, 48
27-32
17-19
11
12
33
34
13
14
Symbol
D0–D10
DRGND
OGND
DGND
DRDY
AGND
CLK+
CLK−
OVR
V
V
V
DR
A
D
Equivalent Circuit
4
The clock input pins can be configured to accept either a single-
ended or a differential clock input signal.
When the single-ended clock mode is selected through CLK_SEL/
DF (pin 8), connect the clock input signal to the CLK+ pin and
connect the CLK− pin to AGND.
When the differential clock mode is selected through CLK_SEL/DF
(pin 8), connect the positive and negative clock inputs to the CLK
+ and CLK− pins, respectively.
The analog input is sampled on the falling edge of the clock input.
Digital data output pins that make up the 11-Bit conversion result.
D0 (pin 20) is the LSB, while D10 (pin 32) is the MSB of the output
word. Output levels are CMOS compatible.
Over-Range Indicator. This output is set HIGH when the input
amplitude exceeds the 11-Bit conversion range (0 to 2047).
Data Ready Strobe. This pin is used to clock the output data. It has
the same frequency as the sampling clock. One word of data is
output in each cycle of this signal. The rising edge of this signal
should be used to capture the output data.
Output GND, internally tied to GND through 5k ohm resistor to
provide pin compatibility with 12 or 14 bit ADCs.
Positive analog supply pins. These pins should be connected to a
quiet +3.3V source and be bypassed to AGND with 0.01 µF and
0.1 µF capacitors located close to the power pins.
The ground return for the analog supply.
Positive digital supply pin. This pin should be connected to a quiet
+3.3V source and be bypassed to DGND with a 0.01 µF and 0.1
µF capacitor located close to the power pin.
The ground return for the digital supply.
Positive driver supply pin for the output drivers. This pin should be
connected to a quiet voltage source of +1.8V and be bypassed to
DRGND with 0.01 µF and 0.1 µF capacitors located close to the
power pins.
The ground return for the digital output driver supply. These pins
should be connected to the system digital ground, but not be
connected in close proximity to the ADC's DGND or AGND pins.
See Section 6.0 (Layout and Grounding) for more details.
Description