stlc1510 STMicroelectronics, stlc1510 Datasheet - Page 34

• Manufacturer Part Number: stlc1510
• Description: Northenlite G.lite Dmt Transceiver
• Manufacturer: STMicroelectronics

STLC1510
Features of MPHY Layer Cell-Level Handshake (Tx
Direction):
Figure 23. UTOPIA Level 2 transmit timing, polling phase and selection phase.
34/40
T x A dd r
T x Clav
Forum Technical Committee’s Utopia Level 1
and Utopia Level 2 specifications, and Chapter
7 of this document, Network Interface and
Controller (NIF).
A single MPHY port at a time is selected for a
cell transmission. However, another MPHY port
may be polled for its TxClav status while the
selected MPHY port transfers data. The ATM
layer polls the TxClav status of a MPHY port by
placing its address on TxAddr. The MPHY port
(STLC1510 device) drives TxClav during each
cycle following one with its address on the
TxAddr lines.
U T xD ata
T x Clk
C ell transm iss ion to:
T x S OC
T x E nb
P 40
1 F
N -1
P 41
N -1
polling
P HY N
1F
P4 2
N + 3
P 43
N + 3
1F
P 44
N + 1
P 45
N + 1
P 46
1 F
Figure 23. depicts the polling phase and the selection
phase of the UTOPIA2 transmit interface. After the
selection of the MPHY port, the cell transfer is exe-
cuted the same way as in UTOPIA Level 1.
The ATM layer selects a MPHY port for transfer
by placing the desired MPHY address onto
TxAddr, when TxEnb is deasserted (high)
during the current clock cycle, and asserted
(low) during the next clock cycle. All MPHY
devices only examine the value on TxAddr for
selection purposes when TxEnb is deasserted
(high). The MPHY port is selected starting from
the cycle after its address is on the TxAddr lines,
and TxEnb is deasserted (high); and ending in
the cycle a new MPHY port is addressed for
selection, and TxEnb is deasserted (high).
N
P 47
N
P 48
se le ctio n
1F
N + 3
N + 3
1F
H 1
N + 1
H 2
po lling
P H Y N + 3
N + 1
1F
H 3
N -1
H 4