pca8533 NXP Semiconductors, pca8533 Datasheet
pca8533
Related parts for pca8533
pca8533 Summary of contents
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... Rev. 1 — 27 April 2011 1. General description The PCA8533 is a peripheral device which interfaces to almost any LCD multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and segments and can easily be cascaded for larger LCD applications ...
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... LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR SCL INPUT FILTERS SDA Fig 1. Block diagram of PCA8533 PCA8533 Product data sheet Description 99 bumps; 5.28 x 1.4 x 0.38 mm Marking codes BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROL PCA8533 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning PCA8533U Viewed from active side. For mechanical details, see Fig 2. Pin configuration for PCA8533U 6.2 Pin description Table 3. Symbol SDAACK SDA SCL CLK V DD SYNC OSC A0, A1 and A2 SA0 LCD BP0, BP1, BP2 and BP3 17, 99, 16 and ...
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... LCD segment or dot matrix displays (see can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCA8533 depend on the required number of active backplane outputs. A selection of display configurations is given in All of the display configurations given in as shown in Fig 3 ...
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... The internal oscillator is selected by connecting pin OSC to V power supplies (pins V 7.1 Power-On Reset (POR) At power-on the PCA8533 resets to the following starting conditions: 1. All backplane outputs are set All segment outputs are set The selected drive mode is: 1:4 multiplex with 4 ...
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... V LCD 2 × on(RMS) All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates Table off RMS on RMS ------------------------ - ----------------------- - V V LCD LCD 0 1 0.354 0.791 0.333 0.745 ...
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... Universal LCD driver for low multiplex rates × 2.449V = ( ) ( off RMS off RMS ( × --------------------- - 2.309V = ( ) off RMS 3 ⁄ 1 when bias is used are dependent on the LCD liquid used. The voltage. LCD PCA8533 (3) LCD ) ), see Figure 5. high (4) (5) © NXP B.V. 2011. All rights reserved ...
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... PCA8533 Product data sheet 100 % OFF SEGMENT Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates V [V] V RMS low high GREY ON SEGMENT ...
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... BP0 off(RMS) Static drive mode waveforms All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (on) (off) mgl745 © NXP B.V. 2011. All rights reserved. ...
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... Rev. 1 — 27 April 2011 Universal LCD driver for low multiplex rates ⁄ ⁄ bias or bias as shown LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms mgl746 at LCD segment. ⁄ 1 bias 2 PCA8533 Figure 7 and © NXP B.V. 2011. All rights reserved ...
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... BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:2 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms mgl747 at LCD segment ...
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... Waveforms for the 1:3 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (b) Resultant waveforms mgl748 at LCD segment. ⁄ 1 bias 3 PCA8533 © NXP B.V. 2011. All rights reserved ...
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... V ( (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates T fr state 1 state 2 mgl749 at LCD segment. ⁄ 1 bias 3 © NXP B.V. 2011. All rights reserved. ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCA8533 are timed by a frequency f which either is derived from the built-in oscillator frequency f frequency clk The clock frequency f calculated as follows ------- - fr Table 6. Nominal clock frequency (Hz) 1536 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to V from pin CLK provides the clock signal for cascaded PCA8533 in the system ...
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... BP0, BP1, BP2, and BP3 respectively. Fig 11. Display RAM bit map showing direct relationship between RAM address and When display data is transmitted to the PCA8533, the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... The subaddress counter is also incremented when the data pointer overflows. In cascaded applications each PCA8533 in the cascade must be addressed separately. Initially, the first PCA8533 is selected by sending the device-select command matching the first device's hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command ...
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... Next the load-data-pointer command is sent to select the preferred display RAM address of the second PCA8533. This last step is very important because during writing data to the first PCA8533, the data pointer of the second PCA8533 is incremented. In addition, the hardware subaddress should not be changed whilst the device is being accessed on the I 7 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates Table Nominal blink frequency of f clk (typical f = 1.536 kHz) clk blinking off 2 1 0.5 © NXP B.V. 2011. All rights reserved. ...
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... The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. By connecting pin SDAACK to pin SDA on the PCA8533, the SDA line becomes fully 2 I C-bus compatible ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 Universal LCD driver for low multiplex rates P STOP condition Figure 15. SLAVE MASTER TRANSMITTER/ TRANSMITTER RECEIVER Figure 16. PCA8533 SDA SCL mbc622 MASTER TRANSMITTER/ RECEIVER mga807 © NXP B.V. 2011. All rights reserved ...
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... The least significant bit of the slave address that a PCA8533 will respond to is defined by the level tied to its SA0 input. The PCA8533 is a write-only device and will not respond to a read access. Having two reserved slave addresses allows the following on the same ...
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... NXP Semiconductors 2 The I C-bus protocol is shown in condition (S) from the I slave addresses available. All PCA8533 whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I ignored by all PCA8533 whose SA0 inputs are set to the alternative level. R slave address ...
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... NXP Semiconductors The command bytes and control bytes are also acknowledged by all addressed PCA8533 connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter; see The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCA8533 ...
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... Table 7 All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates [1] Section 7.14 and Section 7.12. 1:2 multiplex RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 ...
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... SA0, CLK, SYNC, OSC, A0, A1 BP0, BP1, BP2, BP3 S79 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 Universal LCD driver for low multiplex rates DD SS LCD SS PCA8533 SCL, SDA, SDAACK LCD V SS 013aaa281 © ...
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... Ref. 8 “JESD78” All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. ...
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... 0. −0 − [ − 0 − PCA8533 Max Unit 5.5 V 6.5 V 1.6 V μA 20 μ μ 5 5.5 V μ © NXP B.V. 2011. All rights reserved. ...
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... For typical values, see Figure 20. [3] For typical values, see Figure 21. [4] Not tested, design specification only. 2 [5] The I C-bus interface of PCA8533 tolerant. [ backplane capacitance. bpl [ segment capacitance. sgm [8] Outputs measured individually and sequentially. Fig 20. Typical I PCA8533 Product data sheet … ...
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... T amb connected. with respect to V DD(LCD) All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates 001aal524 (V) LCD = 1.536 kHz; all RAM written with logic 1; no display ...
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... Typ [1][2] 960 1536 [1][2] 797 1536 130 - 130 - - - - - - LCD - - 1.3 - 0.6 - 100 - 0 - 1.3 - 0.6 - 0 bus - - PCA8533 Max Unit 3046 Hz 3046 Hz μs - μ μs - μs 30 400 kHz μs - μ μs - μs - μs - μs - μs 0.3 μs 0.3 400 and V with © NXP B.V. 2011. All rights reserved. ...
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... PD(drv BUF LOW t HD;STA C-bus timing waveforms All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates t clk( HD;DAT t HIGH t SU;STA © NXP B.V. 2011. All rights reserved. 0 ...
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... NXP Semiconductors 13. Application information 13.1 Cascaded operation Large display configurations sixteen PCA8533 can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable 2 I C-bus slave address (SA0). Table 19. Cluster 1 2 Cascaded PCA8533 are synchronized. They can share the backplane signals from one of the devices in the cascade ...
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... A PCA8533 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCA8533 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC ...
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... NXP Semiconductors Fig 25. Synchronization of the cascade for the various PCA8533 drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high then the device will not be able to synchronize properly. This is particularly applicable to COG applications. resistance. ...
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... Table 22 the RAM has to be written entirely and BP2/S2, BP2/S5, All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates Table 21 (see ...
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... max 0.020 0.053 mm nom 0.381 0.017 0.050 5.276 1.402 min 0.014 0.047 Note 1. Dimension not drawn to scale Outline version IEC PCA8533-2 Fig 26. Bare die outline of PCA8533-2 PCA8533 Product data sheet 0 detail scale (1) ( 0.289 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates Description [ C-bus acknowledge output [ C-bus serial data input [ C-bus serial clock input ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates Description LCD segment output © NXP B.V. 2011. All rights reserved ...
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... Alignment mark locations X (μm) 2300.5 −2320.2 −2208.3 All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates Description LCD segment output LCD backplane output [2] dummy bump [2] Section 8.1. Y (μm) 55 ...
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... NXP Semiconductors Fig 27. Alignment marks of PCA8533 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. ...
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... NXP Semiconductors 16. Packing information F y Fig 28. Tray details for PCA8533 Table 25. See Figure Symbol PCA8533 Product data sheet 1.1 2.1 3.1 1.2 2.2 1.3 1.y x Tray dimensions 28. Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction ...
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... NXP Semiconductors Fig 29. Tray alignment of PCA8533 The orientation of the pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to Figure 26 17. Abbreviations Table 26. Acronym CMOS COG DC ESD HBM ...
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... NX3-00092 — NXP store and transport requirements [11] UM10204 — I PCA8533 Product data sheet Universal LCD driver for low multiplex rates 2 C-bus specification and user manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors 19. Revision history Table 27. Revision history Document ID Release date PCA8533 v.1 20110427 PCA8533 Product data sheet Universal LCD driver for low multiplex rates Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates © NXP B.V. 2011. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 27 April 2011 PCA8533 Universal LCD driver for low multiplex rates © NXP B.V. 2011. All rights reserved ...
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... Application information . . . . . . . . . . . . . . . . . 33 Cascaded operation RAM writing in 1:3 multiplex drive mode . . . . 36 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 37 Handling information . . . . . . . . . . . . . . . . . . . 41 Packing information . . . . . . . . . . . . . . . . . . . . 42 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 43 References Revision history . . . . . . . . . . . . . . . . . . . . . . . 45 Legal information . . . . . . . . . . . . . . . . . . . . . . 46 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Contact information . . . . . . . . . . . . . . . . . . . . 47 Contents Date of release: 27 April 2011 Document identifier: PCA8533 All rights reserved. ...