pcf8582e-2t NXP Semiconductors, pcf8582e-2t Datasheet - Page 13

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pcf8582e-2t

Manufacturer Part Number
pcf8582e-2t
Description
8-bit Cmos Eeproms With I2c-bus Interface
Manufacturer
NXP Semiconductors
Datasheet

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I
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
V
Note
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
December 1994
2
f
t
t
t
t
t
t
t
t
t
t
t
SYMBOL
IH
SCL
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
HD;DAT
SU;DAT
r
f
SU;STO
C-BUS CHARACTERISTICS
256 x 8-bit CMOS EEPROMS
with I
with an input voltage swing from V
internally provided by a transmitter.
2
C-bus interface
clock frequency
time the bus must be free before new transmission can start
start condition hold time after which first clock pulse is generated
LOW level clock period
HIGH level clock period
set-up time for start condition
data hold time for bus compatible masters
data hold time for bus devices
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for stop condition
SS
PARAMETER
to V
DD
.
13
repeated start
note 1
CONDITIONS MIN. MAX. UNIT
PCX8582X-2 Family
Product specification
0
4.7
4.0
4.7
4.0
4.7
5
0
250
4.7
100
1
300
kHz
ns
ns
ns
IL
s
s
s
s
s
s
s
s
and

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