pcf85134 NXP Semiconductors, pcf85134 Datasheet
pcf85134
Available stocks
Related parts for pcf85134
pcf85134 Summary of contents
Page 1
... The PCF85134 is a peripheral device which interfaces to almost any LCD multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and segments. In addition, the PCF85134 can be easily cascaded for larger LCD applications. The PCF85134 is compatible with most ...
Page 2
... Marking codes Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates Delivery form tape and reel Marking code PCF85134HL © NXP B.V. 2009. All rights reserved. Version SOT315 ...
Page 3
... LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF85134 PCF85134_1 Product data sheet BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROL PCF85134 BLINKER TIMEBASE COMMAND POWER-ON ...
Page 4
... PCF85134 Top view. For mechanical details, see Figure Pin configuration for SOT315-1 (PCF85134) Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates 22. © NXP B.V. 2009. All rights reserved. 60 S10 ...
Page 5
... I C-bus slave address input 0 48 ground supply voltage 49 input of LCD supply voltage LCD segment output Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates © NXP B.V. 2009. All rights reserved ...
Page 6
... LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCF85134 depend on the number of active backplane outputs required. A selection of display configurations is shown in of these configurations can be implemented in the typical system shown in Table 4. Selection of display confi ...
Page 7
... LCD is calculated with on(RMS ----------------------------- - = V LCD Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates and V . The center resistor is bypassed LCD off RMS on RMS -------------------------- ------------------------ - LCD LCD 0 1 0.354 0.791 0.333 ...
Page 8
... Rev. 01 — 17 December 2009 Universal LCD driver for low multiplex rates to V and is determined from off(RMS 2.449V = off RMS off RMS 4 3 2.309V --------------------- - = off RMS 3 1 when bias is used. 3 PCF85134 Equation 2: (2) Equation 3: (3) LCD © NXP B.V. 2009. All rights reserved ...
Page 9
... V ( (t) V (t). state2 ( BP0 off(RMS) Static drive mode waveforms Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates Figure T fr LCD segments state 1 state 2 (on) (off) 013aaa207 © NXP B.V. 2009. All rights reserved ...
Page 10
... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85134 allows the use of Figure 6. Fig 5. PCF85134_1 Product data sheet 1 1 bias LCD V /2 BP0 LCD LCD BP1 V /2 LCD LCD ...
Page 11
... V (t) V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:2 multiplex drive mode with Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms 013aaa209 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved. ...
Page 12
... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:3 multiplex drive mode with Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 013aaa210 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved ...
Page 13
... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:4 multiplex drive mode with Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates T fr state 1 state 2 013aaa211 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved. LCD segments ...
Page 14
... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCF85134 are timed by the frequency f , which equals either the built-in oscillator frequency f clk f . The clock frequency f clk(ext) 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin V output from pin CLK is the clock signal for any cascaded PCF85134 in the system. ...
Page 15
... Fig 9. When display data is transmitted to the PCF85134, the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples. To illustrate the fi ...
Page 16
LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
Page 17
... The subaddress counter is also incremented when the data pointer overflows. In cascaded applications each PCF85134 in the cascade must be addressed separately. Initially, the first PCF85134 is selected by sending the device-select command matching the first device's hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command ...
Page 18
... The SYNC signal resets these sequences to the following starting points: bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex, and bit 0 for static mode. The PCF85134 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row selected for display instead of the contents of row 0 ...
Page 19
... Blink frequency with respect clk - blinking off 2.5 f clk --------- 768 1.3 f clk ----------- - 1536 0.6 f clk ----------- - 3072 Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates clk = 1.970 kHz Table 10). (typical) Unit © NXP B.V. 2009. All rights reserved ...
Page 20
... Product data sheet Universal LCD driver for low multiplex rates 2 C-bus SDA SCL data line stable; data valid S START condition Rev. 01 — 17 December 2009 PCF85134 Figure 11. change of data allowed mba607 Figure 12. P STOP condition © NXP B.V. 2009. All rights reserved. SDA ...
Page 21
... RECEIVER 2 C-bus is illustrated in data output data output by receiver SCL from 1 master S START condition 2 C-bus Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates SLAVE MASTER TRANSMITTER/ TRANSMITTER RECEIVER Figure 14. not acknowledge acknowledge 2 8 clock pulse for acknowledgement MASTER ...
Page 22
... Two I C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF85134. The least significant bit of the slave address is bit R/W. The PCF85134 is a write-only device. It will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defined by the level tied at input SA0. Two displays controlled by PCF85134 can be recognized on the same I • ...
Page 23
... The command bytes and control bytes are also acknowledged by all addressed PCF85134s connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated ...
Page 24
... NXP Semiconductors The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCF85134. After the last display byte, the I Alternatively a START may be issued to RESTART I 8.3 Command decoder The command decoder identifies command bytes that arrive on the I five commands: Table 9. Command ...
Page 25
... For the blink frequencies, see 8.4 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF85134 and coordinates their effects. The controller also loads display data into the display RAM as required by the storage order. PCF85134_1 ...
Page 26
... V DD OSC SYNC A0, A1 LCD BP0, BP1, BP2, BP3 LCD S0 to S59 V SS Rev. 01 — 17 December 2009 PCF85134 SCL V SS SDA LCD V SS 001aah615 © NXP B.V. 2009. All rights reserved ...
Page 27
... Ref. 5 Ref. 6 “JESD22-A115”. Ref. 7 “JESD78” = +85 C). Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. LCD DD [1] ...
Page 28
... pin SDA bpl LCD sgm LCD external clock with 50 % duty factor Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates Min Typ 1.8 - 2 1.0 1.3 1 ...
Page 29
... PCF85134_1 Product data sheet = 2 6 +85 C; unless otherwise specified. LCD amb Conditions LCD . Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates Min Typ [1] 1440 1970 800 - 130 - 130 - - ...
Page 30
... Product data sheet clk t clk(H) CLK SYNC t PD(SYNC_N BUF LOW t HD;STA C-bus timing waveforms Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates t clk(L) t PD(SYNC_N) t SYNC_NL t PD(drv) 001aah618 HD;DAT t HIGH t SU;STA © NXP B.V. 2009. All rights reserved. ...
Page 31
... NXP Semiconductors 13. Application information 13.1 Cascaded operation Large display configurations PCF85134 can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable 2 I C-bus slave address (SA0). Table 18. Cluster 1 2 When cascaded PCF85134 are synchronized, they can share the backplane signals from one of the devices in the cascade ...
Page 32
... A PCF85134 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost restored by the first PCF85134 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal ...
Page 33
... NXP Semiconductors Fig 21. Synchronization of the cascade for various PCF85134 drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, the device will not be able to synchronize properly. Table 19 Table 19. Number of devices ...
Page 34
... Rev. 01 — 17 December 2009 Universal LCD driver for low multiplex rates detail 0.75 1.45 1 0.2 0.15 0.1 0.30 1.05 EUROPEAN PROJECTION PCF85134 SOT315 ( 1.05 0 ISSUE DATE 00-01-19 03-02-25 © NXP B.V. 2009. All rights reserved ...
Page 35
... The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering PCF85134_1 Product data sheet Universal LCD driver for low multiplex rates Rev. 01 — 17 December 2009 PCF85134 © NXP B.V. 2009. All rights reserved ...
Page 36
... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 23. Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates Figure 23) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 ...
Page 37
... Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Integrated Circuit Liquid Crystal Display Machine Model Random Access Memory Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates peak temperature © NXP B.V. 2009. All rights reserved. time 001aac844 ...
Page 38
... Release date PCF85134_1 20091217 PCF85134_1 Product data sheet Universal LCD driver for low multiplex rates 2 C-bus specification and user manual Data sheet status Change notice Product data sheet - Rev. 01 — 17 December 2009 PCF85134 Supersedes - © NXP B.V. 2009. All rights reserved ...
Page 39
... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates © NXP B.V. 2009. All rights reserved ...
Page 40
... Handling information . . . . . . . . . . . . . . . . . . . 35 Soldering of SMD packages . . . . . . . . . . . . . . 35 Introduction to soldering Wave and reflow soldering . . . . . . . . . . . . . . . 35 Wave soldering Reflow soldering Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . 38 Legal information . . . . . . . . . . . . . . . . . . . . . . 39 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Contact information . . . . . . . . . . . . . . . . . . . . 39 Contents Date of release: 17 December 2009 Document identifier: PCF85134_1 All rights reserved. ...