pcf8532 NXP Semiconductors, pcf8532 Datasheet
pcf8532
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pcf8532 Summary of contents
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... Rev. 1 — 10 February 2009 1. General description The PCF8532 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 160 segments and can easily be cascaded for larger LCD applications ...
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... GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF8532 PCF8532_1 Product data sheet Ordering information Package Name Description PCF8532U bare die; 197 bumps; 6.5 Marking codes BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD ...
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... Pinning information 6.1 Pinning PCF8532 Top view. For mechanical details, see Figure Fig 2. Bonding pad location of PCF8532 + 24. 001aah892 ...
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... LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 160 segments. The display configurations possible with the PCF8532 depend on the number of active backplane outputs required. A selection of display configurations is shown in All of the display confi ...
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... The internal oscillator is selected by connecting pin OSC to V power supplies (V 7.1 Power-on reset At power-on the PCF8532 resets to a default starting condition: • All backplane and segment outputs are set to V • The selected drive mode is 1:4 multiplex with • ...
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... LCD off(RMS LCD th 1 bias are possible but the discrimination and 2 2 and is determined from the equation: off(RMS) PCF8532 V on RMS D = -------------------------- V off RMS 2.236 2.236 1.915 1.732 (1) (2) © NXP B.V. 2009. All rights reserved. ...
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... V --------------------- - = 2 LCD LCD off RMS is sometimes referred as the LCD operating voltage. LCD Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates 2.449V = off RMS off RMS 3 2.309V = off RMS 3 1 when bias is used. 3 (3) LCD © ...
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... LCD V ( (t) V (t). state2 (Sn+1) BP0 off(RMS) Static drive mode waveforms Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates Figure T fr LCD segments state 1 state 2 (on) (off) mgl745 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 7.4.2 1:2 multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8532 allows the use of Figure 6. Fig 5. PCF8532_1 Product data sheet 1 1 bias LCD BP0 LCD LCD BP1 LCD V SS ...
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... V (t) V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:2 multiplex drive mode with Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms mgl747 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved. ...
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... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:3 multiplex drive mode with Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 mgl748 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved ...
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... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:4 multiplex drive mode with Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates T fr state 1 state 2 mgl749 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved. LCD segments ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCF8532 are timed by a frequency f which either is derived from the built-in oscillator frequency f external clock frequency f The clock frequency f 7.5.1 Internal clock The internal logic and the LCD drive signals of the PCF8532 are timed either by the built-in oscillator external clock ...
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... RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively. When display data is transmitted to the PCF8532 the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands ...
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... The display RAM bitmap shows the direct relationship between the display RAM addresses and the segment outputs; and between the bits in a RAM word and the backplane outputs. Display RAM bitmap Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates 155 156 157 158 159 Figure © ...
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LCD segments LCD backplanes a S n+2 BP0 n+3 n n+4 n static n n+6 BP0 1 ...
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... Bit 0 for static mode The PCF8532 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of bit selected for display instead of the contents of bit 0. In the 1:2 multiplex drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1 ...
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... The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. By connecting pin SDAACK to pin SDA on the PCF8532, the SDA line becomes fully 2 I C-bus compatible ...
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... Product data sheet SDA SCL data line stable; data valid S START condition MASTER SLAVE TRANSMITTER/ TRANSMITTER/ RECEIVER RECEIVER Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates Figure 11. change of data allowed mba607 Figure 12. P STOP condition SLAVE MASTER TRANSMITTER/ ...
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... START condition 2 C-bus 2 C-bus slave receiver. It does not initiate I 2 C-bus master receiver. The only data output from the PCF8532 are accordance with a binary coding scheme such that C-bus slave address have the same hardware subaddress. Rev. 1 — 10 February 2009 ...
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... C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8532. The least significant bit of the slave address that a PCF8532 responds to is defined by the level tied at its input SA0. The PCF8532 is a write only device and does not respond to a read access. Two types of PCF8532 can be distinguished on the same I allows: • ...
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... Fig 15. I C-bus protocol Fig 16. Format of control byte Table 7. Bit 7.17 Command decoder The command decoder identifies command bytes that arrive on the I commands available to the PCF8532 are defined in PCF8532_1 Product data sheet RAM/command byte RAM DATA ...
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... CLK pin (see Table 10. Bit [1] Power-on and reset value. Table 11. Bit [1] Power-on and reset value. PCF8532_1 Product data sheet Definition of PCF8532 commands Operation code ...
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... Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates 1:2 multiplex RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 [2] [3] © NXP B.V. 2009. All rights reserved. [ ...
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... Power-on and reset value. 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8532 and co-ordinates their effects. The display controller is also responsible for loading display data into the display RAM as required by the filling order. ...
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... V DD SYNC A0 LCD BP0 to BP3 LCD S0 to S159 LCD T1 Rev. 1 — 10 February 2009 PCF8532 SCL V SS SDA V SS SDAACK LCD 001aah856 © NXP B.V. 2009. All rights reserved ...
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... HBM voltage MM latch-up current Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. LCD DD [1] ...
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... SDAACK and SCL on pins BP0 to BP3 and S0 to S159 pins BP0 to BP3 LCD pins S0 to S159 LCD C-bus inactive LCD Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates Min Typ Max 1.8 - 5.5 1.8 - 8.0 [1][ [1] ...
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... MUX 1:4; all RAM written with logic 1; no display connected; external clock with amb f = 1.800 kHz. clk(ext) (typical) with respect to V DD(LCD) Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates 001aaj497 (V) LCD LCD © NXP B.V. 2009. All rights reserved. ...
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... CLK; see Table 15 external clock source used external clock source used LCD of both SDA and SCL signals of both SDA and SCL signals . Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates Min Typ [1] 900 1800 [2] 700 - 100 ...
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... CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv BUF LOW t t HD;STA r 2 C-bus timing waveforms Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates t clk(L) t VD;ACK HD;DAT HIGH t SU;STA © NXP B.V. 2009. All rights reserved ...
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... In the cascaded applications, the OSC pin of the PCF8532 with subaddress 0 is connected to V the CLK pin. The other PCF8532 devices are having the OSC pin connected to V meaning that this devices are ready to receive external clock, the signal being provided by the device with subaddress 0. ...
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... Alternatively the schematic can be also constructed such that all the devices have OSC pin connected to V connected to the same external CLK). A configuration where SYNC is connected but all PCF8532 are using the internal clock (OSC pin tied to V Table 19. Number of devices ...
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... V DD HOST MICRO- PROCESSOR/ MICRO- CONTROLLER V SS (1) Is master (OSC connected to V (2) Is slave (OSC connected to V Fig 22. Cascaded configuration with one PCF8532 and one PCF8533 using the internal PCF8532_1 Product data sheet SDAACK SDA SCL SYNC CLK OSC t r SDAACK ...
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... NXP Semiconductors Fig 23. Synchronization of the cascade for the various PCF8532 drive modes PCF8532_1 Product data sheet Universal LCD driver for low multiplex rates = BP0 SYNC (a) static drive mode BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1:2 multiplex drive mode BP2 (1/3 bias) SYNC ...
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... DIMENSIONS (mm are the original dimensions) UNIT max 0.018 mm nom 0.380 0.015 0.0338 min 0.012 Note 1. Dimension not drawn to scale. OUTLINE VERSION IEC PCF8532U Fig 24. Bare die outline of PCF8532U PCF8532_1 Product data sheet PC8532-1 197 detail scale (1) (1) D ...
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... Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates Symbol Pad S68 100 750.2 S69 101 696.2 S70 102 642.2 S71 103 588.2 S72 104 534 ...
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... Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates Symbol Pad S105 141 1602.2 S106 142 1656.2 S107 143 1710.2 S108 144 1764.2 S109 145 1818 ...
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... Connected to pin S131 S28 S29 S130 Table 22. Alignment marks Size ( m) 121.5 121.5 121.5 121.5 REF S1 Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates Symbol Pad S146 182 2126.7 S147 183 2072.7 S148 184 2018.7 S149 185 1964 ...
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... PC8532-1 Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates Value 8.8 mm 3.6 mm 6.65 mm 1.31 mm 50 ...
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... Indium Tin Oxide Liquid Crystal Display Least Significant Bit Machine Model Most Significant Bit Random Access Memory Root Mean Square Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates © NXP B.V. 2009. All rights reserved ...
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... Revision history Table 25. Revision history Document ID Release date PCF8532_1 20090210 PCF8532_1 Product data sheet Universal LCD driver for low multiplex rates Data sheet status Change notice Product data sheet - Rev. 1 — 10 February 2009 PCF8532 Supersedes - © NXP B.V. 2009. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 1 — 10 February 2009 PCF8532 Universal LCD driver for low multiplex rates © NXP B.V. 2009. All rights reserved ...
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... For sales office addresses, please send an email to: salesaddresses@nxp.com PCF8532 Universal LCD driver for low multiplex rates Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 36 Packing information . . . . . . . . . . . . . . . . . . . . 40 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41 Revision history . . . . . . . . . . . . . . . . . . . . . . . 42 Legal information . . . . . . . . . . . . . . . . . . . . . . 43 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Contact information . . . . . . . . . . . . . . . . . . . . 43 Contents Date of release: 10 February 2009 Document identifier: PCF8532_1 All rights reserved. ...