74lvq374 STMicroelectronics, 74lvq374 Datasheet

no-image

74lvq374

Manufacturer Part Number
74lvq374
Description
Octal D-type Flip-flop With 3 State Outputs Non Inverting
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVQ374
Manufacturer:
ST
0
Part Number:
74lvq374M
Manufacturer:
ST
0
Part Number:
74lvq374TTR
Manufacturer:
ST
0
DESCRIPTION
74LVQ374 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type Flip-Flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
HIGH SPEED:
f
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
LOW NOISE:
V
75 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
IMPROVED LATCH-UP IMMUNITY
MAX
CC
PLH
OH
OLP
CC
= 4 A (MAX.) at T
| = I
(OPR) = 2V to 3.6V (1.2V Data Retention)
= 180 MHz (TYP.) at V
= 0.4V (TYP.) at V
t
PHL
OL
= 12 mA (MIN) at V
A
=25°C
CC
WITH 3 STATE OUTPUTS NON INVERTING
= 3.3V
CC
CC
= 3.3V
= 3.0V
2
MOS
Table 1: Order Codes
outputs will be set to the logic that were setup at
the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
OCTAL D-TYPE FLIP-FLOP
PACKAGE
TSSOP
SOP
SOP
74LVQ374
Rev. 5
74LVQ374MTR
74LVQ374TTR
TSSOP
T & R
1/13

Related parts for 74lvq374

74lvq374 Summary of contents

Page 1

... PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 IMPROVED LATCH-UP IMMUNITY DESCRIPTION 74LVQ374 is a low voltage CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C technology ideal for low power and low noise 3 ...

Page 2

... Figure 2: Input And Output Equivalent Circuit Table 3: Truth Table Don’t Care Z : High Impedance Figure 3: Logic Diagram 2/13 Table 2: Pin Description PIN N° 12, 15, 16, 13, 14, 17 INPUTS SYMBOL NAME AND FUNCTION ...

Page 3

... Supply Voltage (note Input Voltage I V Output Voltage O T Operating Temperature op Input Rise and Fall Time V dt/dv 1) Truth Table guaranteed: 1. from 0. Parameter Parameter = 3.0V (note 2) CC 74LVQ374 Value Unit - 400 mA -65 to +150 ° ...

Page 4

... Table 6: DC Specifications Symbol Parameter V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I High Impedance oz Output Leakage Current I Quiescent Supply CC Current I Dynamic Output OLD Current (note OHD 1) Maximum test duration 2ms, one output loaded at time ...

Page 5

... Max. Min. 7.7 12.0 14.0 6.3 9.0 10.5 8.8 13.0 15.0 7.2 10.0 11.5 9.2 13.0 15.0 7.2 10.0 11.5 1.5 4.0 4.0 1.1 3.0 3.0 0.0 3.0 3.0 0.0 2.0 2.0 0.0 1.0 1.0 0.0 1.5 1.5 150 80 60 180 100 80 0.5 1.0 1.0 0.5 1.0 1 PHLm PHLn Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min CC(opr 74LVQ374 Unit Max. 16.0 ns 12.0 17.0 ns 13.0 17 MHz 1.0 ns 1.0 Unit Max (per Flip IN CC 5/13 ...

Page 6

... Figure 4: Test Circuit PLH PHL PZL PLZ PZH PHZ C = 50pF or equivalent (includes jig and probe capacitance 500 or equivalent pulse generator (typically OUT Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) ...

Page 7

... Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) Figure 7: Waveform - Pulse Width (f=1MHz; 50% duty cycle) 74LVQ374 7/13 ...

Page 8

... DIM. MIN. A 2.35 A1 0.1 B 0.33 C 0.23 D 12. 10.00 h 0.25 L 0.4 k 0° ddd 8/13 SO-20 MECHANICAL DATA mm. TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 1.27 10.65 0.75 1.27 8° 0.100 inch MIN. TYP. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.394 0.010 0.016 0° 0016022D MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.419 0.030 0.050 8° ...

Page 9

... K 0˚ PIN 1 IDENTIFICATION 1 mm. TYP MAX. 1.2 0.15 1 1.05 0.30 0.20 6.5 6.6 6.4 6.6 4.4 4.48 0.65 BSC 8˚ 0.60 0. 74LVQ374 inch MIN. TYP. 0.002 0.004 0.031 0.039 0.007 0.004 0.252 0.256 0.244 0.252 0.169 0.173 0.0256 BSC 0˚ 0.018 0.024 0087225C MAX. 0.047 0.006 0.041 0.012 ...

Page 10

... DIM. MIN 12 10.8 Bo 13.2 Ko 3.1 Po 3.9 P 11.9 10/13 Tape & Reel SO-20 MECHANICAL DATA mm. TYP MAX. 330 13.2 30.4 11 13.4 3.3 4.1 12.1 inch MIN. TYP. 12.992 0.504 0.795 2.362 0.425 0.520 0.122 0.153 0.468 MAX. 0.519 1.197 0.433 0.528 0.130 0.161 0.476 ...

Page 11

... Tape & Reel TSSOP20 MECHANICAL DATA DIM. MIN 12 6.8 Bo 6.9 Ko 1.7 Po 3.9 P 11.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 7 0.268 7.1 0.272 1.9 0.067 4.1 0.153 12.1 0.468 74LVQ374 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.276 0.280 0.075 0.161 0.476 11/13 ...

Page 12

... Table 10: Revision History Date Revision 29-Jul-2004 5 12/13 Description of Changes Ordering Codes Revision - pag. 1. ...

Page 13

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies www.st.com 74LVQ374 13/13 ...

Related keywords