74lvt16500a NXP Semiconductors, 74lvt16500a Datasheet
74lvt16500a
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74lvt16500a Summary of contents
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... V 18-bit universal bus transceiver; 3-state Rev. 03 — 29 May 2006 1. General description The 74LVT16500A is a high-performance BiCMOS product designed for V 3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data fl ...
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... B10 A10 16 B11 A11 17 B12 A12 19 B13 A13 20 B14 A14 21 B15 A15 23 B16 A16 24 B17 A17 26 001aaf038 Rev. 03 — 29 May 2006 74LVT16500A 1 OEAB EN1 55 CPAB 2C3 2 LEAB OEBA EN4 30 CPBA 5C6 28 LEBA ...
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... Fig 3. Logic diagram 74LVT16500A_3 Product data sheet 3.3 V 18-bit universal bus transceiver; 3-state 1 OEAB 55 CPAB 2 LEAB 28 LEBA 30 CPBA 27 OEBA CLK to 17 other channels Rev. 03 — 29 May 2006 74LVT16500A CLK 001aaf035 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... OEBA LEBA 28 Pin description Pin Description 1 A-to-B output enable input 2 A-to-B latch enable input 3 data input/output A0 4 ground ( data input/output A1 6 data input/output A2 7 supply voltage Rev. 03 — 29 May 2006 74LVT16500A 56 GND 55 CPAB GND ...
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... B10 42 data input/output B9 43 data input/output B8 44 data input/output B7 45 data input/output B6 46 ground ( data input/output B5 48 data input/output B4 Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... LEAB OEBA LEBA Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Input Internal register CPAB An CPBA ...
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... HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current none current duty cycle f 1 kHz i input transition rise and outputs enabled fall rate ambient temperature in free air Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Min 0.5 [1] 0.5 [1] 0 [2] ...
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... HIGH-state when OEAB or OEBA don’t care 3 GND outputs HIGH-state outputs LOW-state outputs disabled Rev. 03 — 29 May 2006 74LVT16500A Min Typ - 0. 2.4 2.55 2.0 2.3 - 0.07 - 0.3 - 0.25 - 0.3 - 0.36 [2] or GND - 0 ...
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... Figure 7 see Figure 5 see Figure 6 see Figure 7 see Figure 8 see Figure 9 Figure 8 Figure 9 see Figure 10 see Figure 10 see Figure 10 Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Min Typ [7] - 0.1 or GND 1 GND. CC 11. Min Typ ...
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... Figure 5 see Figure 6 see Figure 7 see Figure 5 see Figure 6 see Figure 7 see Figure 8 see Figure 9 Figure 8 Figure 9 see Figure 10 see Figure 10 see Figure 10 see Figure 10 see Figure 10 see Figure 10 Rev. 03 — 29 May 2006 74LVT16500A 11. Min Typ Max ...
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... output Measurements points are given in Table V and V are typical voltage output drop that occur with the output load Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 11. Min Typ Max ...
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... I input OEAB V OH output Measurements points are given in Table V is typical voltage output drop that occur with the output load. OH Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 1/f max PLH 001aaf037 8 ...
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... Measurements points are given in Table The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points Input Output 1.5 V 1.5 V 1.5 V 1.5 V Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state PZL PLZ 001aad346 8. ...
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... Termination resistance should be equal to output impedance Test voltage for switching times. EXT Test data MHz 500 ns 2.5 ns Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state EXT ...
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... Product data sheet 2.5 scale (1) ( 0.28 0.2 0.2 14.1 6.2 0.5 0.17 0.1 0.1 13.9 6.0 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state detail 8.3 0.8 0.50 1 0.25 0.08 7.9 0.4 0.35 EUROPEAN PROJECTION © ...
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... scale (1) ( 0.3 0.22 18.55 7.6 10.4 0.635 0.2 0.13 18.30 7.4 10.1 REFERENCES JEDEC JEITA MO-118 Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state detail 1.0 1.2 1.4 0.25 0.18 0.1 0.6 1.0 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...
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... JEDEC JC40.2 Std 17 with JESD78 diagram”: corrected clock names and pin names characteristics”: splitting up t Product specification Product specification Product specification Rev. 03 — 29 May 2006 74LVT16500A Change notice Supersedes - 74LVT16500A_2 and t parameter ‘An to LEAB or Bn su(H) su(L) - 74LVT16500A_1 - 74LVT16500A - - © ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 03 — 29 May 2006 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. All rights reserved. Date of release: 29 May 2006 Document identifier: 74LVT16500A_3 ...