74lvth32245ec NXP Semiconductors, 74lvth32245ec Datasheet

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74lvth32245ec

Manufacturer Part Number
74lvth32245ec
Description
74lvth32245 3.3 V 32-bit Bus Transceiver; 3-state
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
3. Ordering information
Table 1.
Type number
74LVTH32245EC
Ordering information
Package
Temperature range Name
40 C to +85 C
The 74LVTH32245 is a high-performance BiCMOS product designed for V
3.3 V. The 74LVTH32245 is a 32-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. The device features four output
enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction
control. Pin nOE controls the outputs so that the buses are effectively isolated. Bus hold
on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
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74LVTH32245
3.3 V 32-bit bus transceiver; 3-state
Rev. 01 — 23 January 2008
32-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
ESD protection:
N
N
N
JESD78 Class II level A exceeds 500 mA
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
LFBGA96 plastic low profile fine-pitch ball grid array package;
Description
96 balls; body 13.5
5.5
1.05 mm
Product data sheet
CC
operation at
Version
SOT536-1

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74lvth32245ec Summary of contents

Page 1

... HBM JESD22-A114E exceeds 2000 JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVTH32245EC +85 C Description LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 Product data sheet operation at CC Version SOT536-1 5 ...

Page 2

... NXP Semiconductors 4. Functional diagram 1DIR A3 1A0 A5 1A1 A6 1A2 B5 1A3 B6 1A4 C5 1A5 C6 1A6 D5 1A7 D6 3DIR J3 3A0 J5 3A1 J6 3A2 K5 3A3 K6 3A4 L5 3A5 L6 3A6 M5 3A7 M6 Fig 1. Logic symbol 74LVTH32245_1 Product data sheet 3.3 V 32-bit bus transceiver; 3-state 2DIR H3 1OE A4 2A0 E5 1B0 A2 2A1 E6 1B1 A1 2A2 F5 1B2 ...

Page 3

... NXP Semiconductors V CC 001aah682 Fig 2. Schematic of each output 5. Pinning information 5.1 Pinning 6 1A1 1A3 5 1A0 1A2 4 1OE GND 3 1DIR GND 2 1B0 1B2 1 1B1 1B3 A B Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol nDIR ( nOE ( 1A[0:7] 1B[0:7] 2A[0:7] 2B[0:7] 3A[0:7] 3B[0:7] 4A[0:7] 74LVTH32245_1 ...

Page 4

... NXP Semiconductors Table 2. Pin description …continued Symbol 4B[0:7] GND Functional description [1] Table 3. Function selection Input nOE nDIR [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I I HIGH-level output current OH I LOW-level output current OL T ambient temperature amb t/ V input transition rise and fall rate P total power dissipation tot [1] Above 70 C the value of P derates linearly with 1 ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I bus hold LOW current BHL I bus hold HIGH current BHH I bus hold LOW overdrive BHLO current I bus hold HIGH overdrive BHHO current I supply current CC I additional supply current ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Symbol Parameter t OFF-state to LOW propagation PZL delay t HIGH to OFF-state propagation PHZ delay t LOW to OFF-state propagation PLZ delay [1] All typical values are 3.3 V and T CC 11. Waveforms Measurement points are given in ...

Page 8

... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. enable and disable times Table 8. Measurement points Supply voltage ...

Page 9

... NXP Semiconductors Test data is given in Table 9. Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 7. Load circuitry for switching times Table 9 ...

Page 10

... NXP Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.41 1.2 0.51 mm 1.5 0.31 0.9 0.41 OUTLINE VERSION ...

Page 11

... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74LVTH32245_1 20080123 74LVTH32245_1 Product data sheet 3.3 V 32-bit bus transceiver ...

Page 12

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 13

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations ...

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