74lvc3g07dp NXP Semiconductors, 74lvc3g07dp Datasheet

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74lvc3g07dp

Manufacturer Part Number
74lvc3g07dp
Description
Triple Buffer With Open-drain Output
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The 74LVC3G07 provides three non-inverting buffers.
The output of the device is an open drain and can be connected to other open-drain
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
74LVC3G07
Triple buffer with open-drain output
Rev. 04 — 21 May 2007
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
ESD protection:
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
24 mA output drive (V
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V).
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

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74lvc3g07dp Summary of contents

Page 1

Triple buffer with open-drain output Rev. 04 — 21 May 2007 1. General description The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open drain and can be connected to other open-drain outputs to implement ...

Page 2

... Ordering information Table 1. Ordering information Type number Package Temperature range 74LVC3G07DP +125 C 74LVC3G07DC +125 C 74LVC3G07GT +125 C 74LVC3G07GM +125 C 4. Marking Table 2. Marking codes Type number 74LVC3G07DP 74LVC3G07DC 74LVC3G07GT 74LVC3G07GM 5. Functional diagram mnb136 Fig 1 ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LVC3G07 GND 4 001aab022 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 6. Pin configuration SOT902-1 (XQFN8) 74LVC3G07_4 Product data sheet Fig 5. Pin configuration SOT833-1 (XSON8) 74LVC3G07 ...

Page 4

... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1 and SOT833 GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level high-impedance OFF-state. 8. Limiting values Table 5. ...

Page 5

... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +125 C amb V HIGH-level input IH voltage V LOW-level input IL voltage V LOW-level output OL voltage I input leakage current I I OFF-state output OZ current I power-off leakage OFF current I supply current ...

Page 7

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay nA to nY; see power dissipation V = GND capacitance [1] Typical values are measured the same as t and t ...

Page 8

... NXP Semiconductors Table 9. Measurement points Supply voltage Input 1. 1.95 V 0.5 2 2.7 V 0.5 2.7 V 1 3.6 V 1 5.5 V 0.5 Test data is given in Table 10. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance Z ...

Page 9

... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 10

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 12

... NXP Semiconductors XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 0.15 1.55 OUTLINE VERSION IEC SOT902 Fig 12 ...

Page 13

... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type number 74LVC3G07GM (XQFN8/SOT902-1 package). • ...

Page 14

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 15

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Abbreviations ...

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