tda7333 STMicroelectronics, tda7333 Datasheet
tda7333
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tda7333 Summary of contents
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... Figure 1. Package Table 1. Order Codes Part Number TDA7333 3.3V POWER SUPPLY, 0.35 µm CMOS I TECHNOLOGY 2 Description The TDA7333 is a RDS/RDBS signal processor, intended for recovering the inaudible RDS/RBDS informations which are transmitted on most FM ra- dio broadcasting stations. Cxti Cxto Cref 16pF 16pF XTI ...
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... Chip Select (1=I2C mode, 0=SPI mode) 15 INTN Interrupt output (active low), prog. at buff.not empty,buff. full, block A,B,D ,TA, TA EON 16 MPX Multiplex Input Signal 2/21 VDDA MPX 1 16 REF3 2 15 INTN REF2 3 14 CSN REF1 4 13 SA_DATAOUT TDA7333 VSS SDA_DATAIN SCL_CLK VDDD XTO 7 10 XTI 8 9 Function ...
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... VDDA/VDDD = 3.3V, fosc = 8.55 MHz) Parameter Min. 3.0 - mode Test Conditions 5V tolerant inputs 5V tolerant output buffers in tri-state Test Conditions =5.5V o TDA7333 Values Unit Typ. Max. 3.3 3.6 V +85 °C 8.55 or MHz 8.664 mVrms 750 mVrms 1 MHz 400 kHz Values Min ...
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... TDA7333 6.3 Electrical Characteristics T = -40 to +85 ° amb DDA DDD V and V must not differ more than 0.15 V DDD DDA Table 6. Electrical Characteristics Symbol Parameter Supply (pin 1,5,7) V Digital Supply Voltage DDD V Analog Supply Voltage DDA I Digital Supply Current DDD I Analog Supply Current DDA ...
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... The oversampled data delivered from the modulator are decimated by a value of 16 with a 4th order Sinc Filter. This is considered to be the optimum solution for high decimation factors and for a 3rd order sigma delta mod- ulator. Test Conditions Min. -0.5 53.0 450 450 500 500 0 1000 200 200 TDA7333 Values Unit Typ. Max. +0 kHz - 400 kHz 1 ...
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... TDA7333 The architecture is a very economical implementation because digital multipliers are not required imple- mented by cascading 4 integrators operating at full sampling rate (XTI/2) followed by 4 differentiators operating at the reduced sampling rate (XTI/2/16). Also wrap around logic is allowed and the internal overflow will not af- fect the output signal as long as a minimum required bit width is maintained ...
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... ARI signal. Four biquads are cascaded working at a common sampling frequency of XTI/2/16. Figure 6. Transfer Function of RDS Bandpass Filter 100 4 4.5 Sinc4/16 Transfer Function (RDS Band) 5.6 5.7 5.8 Frequency [Hz] Transfer Function of RDS Filter 5 5.5 6 6.5 Frequency [Hz] TDA7333 5 7/21 ...
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... TDA7333 Figure 7. Phase Response of the RDS Bandpass Filter 5.6 The output sample of the bandpass filter is picked up from a linear interpolator with sinc2 characteristics. The interpolation factor is 32. A zero cross detection is simply formed by taking the sign bit of the interpolated signal. This signal which contains only phase informations is processed by the RDS Demodulator. ...
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... Both PLL are set to the fastest time constant, which is automatically increased to the slowest one. This is done in four steps within a total time of 215.6ms (256 RDS clocks). b: Software selected time constant - In this case the time constant of both PLL can be selected individually by software.PLL time constants can be set independently. TDA7333 9/21 ...
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... TDA7333 7.6 Group and block synchronization module The group and block synchronization module has the following features : – Hardware group and block synchronization – Hardware error detection – Hardware error correction using the quality bit information of the demodulator – Hardware synchronization flywheel – ...
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... RDS block low byte of current RDS block frequency, quality sensitivity, plls setting sinc4 filter settings (for internal use only) test modes (for internal use only) TDA7333 function in I2C mode (CSN=1) SCL (serial clock) SDA (data line) SA (slave address) ...
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... TDA7333 bit 7 bit 6 bit 5 bit 4 bit lue bit rite bne ar_res synch itsrc2 r cce ss r r/w (1) interrupt source itsrc2 itsrc1 no interrupt lock 0 0 block block block ...
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... RDS 16bits information bit 4 of the actual RDS 16bits information bit 3 of the actual RDS 16bits information bit 2 of the actual RDS 16bits information bit 1of the actual RDS 16bits information bit 0 of the actual RDS 16bits information TDA7333 13/21 ...
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... TDA7333 rds_bd_ctrl bit 7 bit 6 bit 5 bit 4 bit lue bit nam e freq qsens1 qsens0 pllb1 pllb0 r/w r/w r/w r/w r/w a cce ss (1) pllf lock tim e needed for 90 deg deviation (2) pllb1 pllb0 lock tim e needed for 90 deg deviation (reset status) ...
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... ACK DATA ACK rds_int trl S = start condition W = write mode Slave address = 001000S ( where S is the level of the pin A = acknowledge bit P = stop condition rds_int[7:0] ACK ACK TDA7333 1 DATA STOP ACK/ACK CONDITION sinc4reg A testreg A P SA_DATAOUT) rds_bd_ctrl[7:0] ACK ...
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... TDA7333 8.2 Read transfer 2 Figure 13 read transfer S S lave addre from master to slave from slave to master Eight bytes can be read at a time (please refer to the to the pages ??? to ??? for the meaning of each bit). The master has always the possibility to read less than eight registers by not sending the acknowledge bit and then generating a stop condition after having read the needed amount of registers ...
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... Figure 17. write rds_int and rds_bd_ctrl registers in spi mode,reading RDS data and related flags CSN CLK DATAIN rds_int[7:0] DATAOUT odv rds_int[5] rds_int[4] rds_int[3] rds_int[2] rds_int[1] rds_int[0] rds_bd_ctrl[7:0] rds_qu[7:0] rds_corrp[7:0] rds_bd_h[7:0] TDA7333 csh 63 64 rds_int[1] rds_int[0] testreg[1] testreg[0] update of registers with shiftregister content if requested {1,rds_int[6:0]} rds_bd_l[7:0] 17/21 ...
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... TDA7333 Figure 18. read out RDS data and related flags, no update of rds_int and rds_bd_ctrl registers CSN CLK DATAIN rds_int[7:0] DATAOUT Figure 19. write rds_int registers in spi mode,reading 1 register CSN CLK DATAIN DATAOUT The content of the rds registers is clocked out on DATAOUT pin in the following order: rds_int[7:0], rds_qu[7:0], rds_corrp[7:0], rds_bd_l[7:0], rds_bd_h[7:0], rds_ctrl[7:0], sinc4reg[7:0], testreg[7:0] For the meaning of the single bits please refer to the pages ...
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... MIN. TYP. MAX. MECHANICAL DATA 0.047 0.002 0.006 0.031 0.039 0.041 0.007 0.012 0.005 0.009 0.114 0.118 0.122 0.244 0.252 0.260 0.170 0.173 0.177 0.026 0.018 0.024 0.030 0.039 0.004 TDA7333 OUTLINE AND TSSOP16 (Body 4.4mm) 0080338 (Jedec MO-153-AB) 19/21 ...
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... TDA7333 11 Revision History Table 9. Revision History Date Revision January 2005 1 20/21 Description of Changes First Issue ...
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