adf4212l Analog Devices, Inc., adf4212l Datasheet - Page 19

• Manufacturer Part Number: adf4212l
• Description: Dual Low Power Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

Interfacing
The ADF4212L has a simple SPI compatible serial interface for
writing to the device. SCLK, SDATA, and LE control the data
transfer. When LE (Latch Enable) goes high, the 22 bits that
have been clocked into the input register on each rising edge of
SCLK will get transferred to the appropriate latch. See Figure 1
for the Timing Diagram and Table I for the Latch Truth Table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz or one update every 1.1 µs. This is certainly more than
adequate for systems that will have typical lock times in hun-
dreds of microseconds.
ADuC812 Interface
Figure 9 shows the interface between the ADF4212L and the
ADuC812 microconverter. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4212L needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the microconverter to the device. When the third byte has
been written, the LE input should be brought high to complete
the transfer.
On first applying power to the ADF4212L, four writes (one
each to the R counter latch and the AB counter latch for both
IF and RF side) are required for the output to become active.
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maxi-
mum rate at which the output frequency can be changed will
be 180 kHz.
REV. A
–19–
ADSP-2181 Interface
Figure 10 shows the interface between the ADF4212L and the
ADSP-21xx Digital Signal Processor. As previously discussed,
the ADF4212L needs a 24-bit serial word for each latch write.
The easiest way to accomplish this using the ADSP-21xx family
is to use the Autobuffered Transmit Mode of operation with
Alternate Framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated. Set
up the word length for eight bits and use three memory loca-
tions for each 24-bit word. To program each 24-bit latch, store
the three 8-bit bytes, enable the Autobuffered Mode, and then
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
Figure 10. ADSP-21xx to ADF4212L Interface
Figure 9. ADuC812 to ADF4212L Interface
ADSP-21xx
ADuC812
I/O PORTS
I/O FLAGS
SCLK
SCLK
MOSI
TFS
DT
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4212L
ADF4212L
ADF4212L