74hct534 NXP Semiconductors, 74hct534 Datasheet
74hct534
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74hct534 Summary of contents
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... Rev. 03 — 18 October 2004 1. General description The 74HCT534 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HCT534 is specified in compliance with JEDEC standard no. 7A. The 74HCT534 is an octal D-type flip-flop featuring separate D-type inputs for each fl ...
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... FF1 FF8 Rev. 03 — 18 October 2004 74HCT534 Version SOT146-1 SOT163 3-STATE Q4 12 OUTPUTS mgm957 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... V octal D-type flip-flop; positive-edge trigger; inverting; 3-state mgm955 Fig 3. IEC logic symbol Rev. 03 — 18 October 2004 74HCT534 mgm956 ...
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... V) 11 clock input (LOW-to-HIGH, edge-triggered) 12 3-state output 13 data input 14 data input 15 3-state output 16 3-state output 17 data input 18 data input 19 3-state output 20 supply voltage Rev. 03 — 18 October 2004 74HCT534 534 001aab843 © ...
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... GND current CC storage temperature power dissipation DIP20 package SO20 package derates linearly with 12 mW/K. tot derates linearly with 8 mW/K. tot Recommended operating conditions Parameter Conditions supply voltage input voltage Rev. 03 — 18 October 2004 74HCT534 Internal flip-flops Min 0.5 > 0.5 V ...
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... GND Rev. 03 — 18 October 2004 74HCT534 …continued Min Typ 6.0 and Min Typ 2.0 1.6 - 1.2 4.4 4.5 3.98 4. 0. GND 125 - 90 - ...
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... 2.1 V; other inputs GND 4 5 pin OE pin CP pins pF; see Figure 9 L Conditions see Figure pF pF see Figure 7 Rev. 03 — 18 October 2004 74HCT534 Min Typ - - or GND 2 4.5 V 4 ...
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... Figure 6 see Figure 6 see Figure 7 see Figure 7 see Figure 6 see Figure 6 see Figure 8 see Figure 8 see Figure where 1.5 V. Rev. 03 — 18 October 2004 74HCT534 Min Typ - 4 [1] [ ...
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... V OE input PLZ Qn output LOW-to-OFF OFF-to-LOW t PHZ Qn output HIGH-to-OFF OFF-to-HIGH outputs enabled GND Rev. 03 — 18 October 2004 74HCT534 max t PLH t t TLH THL mgm959 PZL PZH outputs outputs enabled ...
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... Dn input V Qn output GND PULSE GENERATOR Definitions test circuits Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance (See L Rev. 03 — 18 October 2004 74HCT534 mgm960 D.U.T. ...
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... V octal D-type flip-flop; positive-edge trigger; inverting; 3-state scale (1) ( 1.73 0.53 0.36 26.92 6.40 1.30 0.38 0.23 26.54 6.22 0.068 0.021 0.014 1.060 0.25 0.051 0.015 0.009 1.045 0.24 REFERENCES JEDEC JEITA MS-001 SC-603 Rev. 03 — 18 October 2004 74HCT534 3.60 8.25 10.0 2.54 7.62 3.05 7.80 8.3 0.14 0.32 0.39 0.1 0.3 0.12 0.31 ...
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... 0.49 0.32 13.0 7.6 10.65 1.27 0.36 0.23 12.6 7.4 10.00 0.019 0.013 0.51 0.30 0.419 0.05 0.014 0.009 0.49 0.29 0.394 REFERENCES JEDEC JEITA MS-013 Rev. 03 — 18 October 2004 74HCT534 detail 1.1 1.1 1.4 0.25 0.25 0.4 1.0 0.043 0.043 0.055 0.01 0.01 0.016 0.039 EUROPEAN PROJECTION © ...
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... V octal D-type flip-flop; positive-edge trigger; inverting; 3-state Data sheet status Change notice Product data sheet - Product specification - Rev. 03 — 18 October 2004 74HCT534 Doc. number Supersedes 9397 750 13817 74HC_HCT534_ CNV_2 - 74HC_HCT534_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Rev. 03 — 18 October 2004 74HCT534 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands 74HCT534 Date of release: 18 October 2004 Document number: 9397 750 13817 ...