mm74hc240wmx-nl Fairchild Semiconductor, mm74hc240wmx-nl Datasheet

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mm74hc240wmx-nl

Manufacturer Part Number
mm74hc240wmx-nl
Description
Mm74hc240 Inverting Octal 3-state Buffer
Manufacturer
Fairchild Semiconductor
Datasheet
© 2005 Fairchild Semiconductor Corporation
MM74HC240WM
MM74HC240SJ
MM74HC240MTC
MM74HC240N
MM74HC240
Inverting Octal 3-STATE Buffer
General Description
The MM74HC240 3-STATE buffer utilizes advanced sili-
con-gate CMOS technology. It possesses high drive cur-
rent outputs which enable high speed operation even when
driving large bus capacitances. These circuits achieve
speeds comparable to low power Schottky devices, while
retaining the advantage of CMOS circuitry, i.e., high noise
immunity and low power consumption. It has a fanout of 15
LS-TTL equivalent inputs.
The MM74HC240 is an inverting buffer and has two active
LOW enables (1G and 2G). Each enable independently
controls 4 buffers.
All inputs are protected from damage due to static dis-
charge by diodes to V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
CC
Top View
MTC20
and ground.
M20D
M20B
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS005020
Features
Truth Table
H
L
Z
Typical propagation delay: 12 ns
3-STATE outputs for connection to system buses
Wide power supply range: 2–6V
Low quiescent supply current: 80
Output current: 6 mA
LOW Level
HIGH Impedance
HIGH Level
Package Description
1G
H
H
L
L
1A
H
H
L
L
1Y
H
L
Z
Z
September 1983
Revised May 2005
2G
H
H
L
L
P
A (74 Series)
www.fairchildsemi.com
2A
H
H
L
L
2Y
H
Z
Z
L

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mm74hc240wmx-nl Summary of contents

Page 1

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View © 2005 Fairchild Semiconductor Corporation Features Typical propagation delay 3-STATE outputs for connection to system buses Wide power supply range: 2– ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage ( OUT Clamp Diode Current ( ...

Page 4

AC Electrical Characteristics Symbol Parameter Maximum Propagation Delay PHL PLH Maximum Enable Delay PZH PZL to Active Output t , ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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