mm74hc139 Fairchild Semiconductor, mm74hc139 Datasheet

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mm74hc139

Manufacturer Part Number
mm74hc139
Description
Dual 2-to-4 Line Decoder
Manufacturer
Fairchild Semiconductor
Datasheet

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© 1999 Fairchild Semiconductor Corporation
MM74HC139M
MM74HC139SJ
MM74HC139MTC
MM74HC139N
MM74HC139
Dual 2-To-4 Line Decoder
General Description
The MM74HC139 decoder utilizes advanced silicon-gate
CMOS technology, and is well suited to memory address
decoding or data routing applications. It possesses the
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet has speeds compara-
ble to low power Schottky TTL logic.
The MM74HC139 contain two independent one-of-four
decoders each with a single active low enable input (G1, or
G2). Data on the select inputs (A1, and B1 or A2, and B2)
cause one of the four normally high outputs to go LOW.
The decoder’s outputs can drive 10 low power Schottky
TTL equivalent loads, and are functionally as well as pin
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Pin Assignments for DIP, SOIC, SOP and TSSOP
Package Number
MTC16
M16D
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP) JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS005311.prf
equivalent to the 74LS139. All inputs are protected from
damage due to static discharge by diodes to V
ground.
Features
Truth Table
H
L
X
Typical propagation delays —
Select to outputs (4 delays): 18 ns
Select to output (5 delays): 28 ns
Enable to output: 20 ns
Low power: 40 W quiescent supply power
Fanout of 10 LS-TTL devices
Input current maximum 1 A, typical 10 pA
LOW Level
Don't Care
HIGH Level
Enable
Package Description
G
H
L
L
L
L
Inputs
B
H
H
X
L
L
Select
A
H
H
X
L
L
Y0
September 1983
Revised February 1999
H
H
H
H
L
Y1
Outputs
H
H
H
H
L
www.fairchildsemi.com
Y2
H
H
H
H
L
Y3
H
H
H
H
CC
L
and

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mm74hc139 Summary of contents

Page 1

... CMOS circuitry, yet has speeds compara- ble to low power Schottky TTL logic. The MM74HC139 contain two independent one-of-four decoders each with a single active low enable input (G1, or G2). Data on the select inputs (A1, and B1 or A2, and B2) cause one of the four normally high outputs to go LOW. The decoder’ ...

Page 2

Logic Diagram www.fairchildsemi.com ( ...

Page 3

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Clamp Diode Current ( Output Current, per pin (I ) OUT DC ...

Page 4

AC Electrical Characteristics Symbol Parameter Maximum Propagation PHL PLH Delay, Binary Select to any Output 4 levels of delay t ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Small Outline Package (SOP) EIAJ TYPE II, 5.3mm Wide Package Number M16A Package Number M16D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC16 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...

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