vsc880 Vitesse Semiconductor Corp, vsc880 Datasheet - Page 10

• Manufacturer Part Number: vsc880
• Description: High Performance 16x16 Serial Crosspoint Switch Semiconductor Corporation
• Manufacturer: Vitesse Semiconductor Corp

High Performance 16x16
Serial Crosspoint Switch
Page 10
1.5 Parallel CPU Interface
registers described above. This is an asynchronous interface that was design to operate with many common micro
controllers that are available. The functional timing diagrams for a write and a read are shown in the following
figures. Timing information can be found in the AC Characteristics section of this data sheet.
1.6 Parallel Configuration Interface
switch matrix can be reprogrammed in 4 word clocks by setting the CEN signal LOW. If CEN is set LOW, the
parallel interface DATA[15:0] contains a 16 bit switch configuration input port, the inputs FI[3:0] load the FI bits and
the WEN signal becomes a programming signal as shown in the figure below. It takes 4 word clocks to load all 64 bits
of switch configuration data and 16 FI bits into holding registers. All data transfer timing is relative to REFCLK.
After data has been loaded, and if CCLK is HIGH, all 80 bits of data are strobed into the switch matrix and FI control
logic. Otherwise, the configuration information is stored in holding registers until the next CCLK pulse strobes it in.
Since the CCLK signal is delayed internally in the switch, it can be asserted as early as the WEN signal pulse to
strobe in the configuration information.
FI[15:0]Force IDLE register, bit 0 is channel 0 etc
RESY[15:0]Resynch register, bit 0 is channel 0 etc
OE[15:0]Output enable register, bit 0 is channel 0 etc
LPBK[15:0]Facility loopback register, bit 0 is channel 0 etc
There is a parallel 8 bit CPU interface on the VSC880 that can be used to read and write the status and control
In addition to reading and writing the switch configuration using the CPU interface as described above, the entire
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CWEN
CWEN
ADDR
ADDR
CSEL
CSEL
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Figure 2: CPU Interface Functional Write Cycle Timing
Figure 3: CPU Interface Functional Read Cycle Timing
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
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SEMICONDUCTOR CORPORATION
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Internet: www.vitesse.com
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Hi-Z
Data Sheet
VSC880
G52191-0, Rev 4.2
01/05/01