z90365 ZiLOG Semiconductor, z90365 Datasheet - Page 4

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z90365

Manufacturer Part Number
z90365
Description
Digital Television Controller
Manufacturer
ZiLOG Semiconductor
Datasheet
PIN DESCRIPTION (Continued)
Z90365
Digital Television Controller
Notes:
4
PWM10, PWM9
1. SCL I/O pin is shared with Port 0 or Port 11.
2. SCD I/O pin is shared with Port 02 or Port 12.
3. Half Blank output is a function shared with Port 0F.
4. Digital RGB outputs and the internal SCLK are shared with Port 1 [5:0].
5. Internal processor SCLK is shared with Port 16.
RGB Digital
PWM[5:1]
Port0[F:0]
Port1[8:0]
HalfBlank
PWM outputs are push/pull
ADC[4:0]
HSYNC
VSYNC
Outputs
XTAL1
XTAL2
/Reset
Name
V[3:1]
SCLK
Blank
GND
SCD
IRIN
SCL
LPF
V
CC
8-Bit Pulse Width Modulator
OSD Video Output Typically
Outputs of the RGB Matrix
Drive B, G, and R Outputs
4-Bit A/D Converter Input
Infrared Remote Capture
R[1:0], G[1:0], and B[1:0]
Internal Processor SCLK
Crystal Oscillator Output
Crystal Oscillator Input
OSD HalfBlank Output
14-Bit Pulse Width
OSD Blank Output
Input/Output Ports
Input/Output Ports
Bit Programmable
Bit Programmable
Modulator Output
Device Reset
I
I
2
2
Loop Filter
C Clock I/O
Function
H_SYNC
C Data I/O
V_SYNC
+ 5 Volts
0 Volts
Output
Input
Table 1. 42-Pin SDIP Pin Identification
16, 12, 20, 19, 18, 17,
37, 14, 17, 16, 19, 18
P R E L I M I N A R Y
21, -, -, -, -, -, 38, 37,
35, -, -, 15, 8, 40, 39,
9, 10, 11, 12, 28
3, 4, 5, 6, 7
42, 41, 14
22, 23, 24
39 or 41
40 or 42
Z90365
13, 30
1, 2
34
36
11
31
32
29
26
27
33
25
21
20
Direction
PWR
PWR
BOD
BOD
AO
AB
AI
AI
O
O
O
O
O
O
O
B
B
B
B
I
I
Reset
O
O
O
O
O
O
I
I
I
I
I
I
I
I
CP97TEL2800
Notes
1
2
3
4
5
6
Zilog

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