fs6128-07 AMI Semiconductor, Inc., fs6128-07 Datasheet - Page 2

• Manufacturer Part Number: fs6128-07
• Description: Fs6128-07 Pll Clock Generator Ic With Vcxo
• Manufacturer: AMI Semiconductor, Inc.

FS6128-07
FS6128-07
FS6128-07
FS6128-07
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
DO = Digital Output; P = Power/Ground; # = Active Low pin
3.0
3.1
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6128 system components.
Loading capacitance for the crystal is internal to the
FS6128. No external components (other than the reso-
nator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accom-
plished by varying the voltage on the XTUNE pin. The
value of this voltage controls the effective capacitance
presented to the crystal. The actual amount that this load
capacitance change will alter the oscillator frequency de-
pends on the characteristics of the crystal as well as the
oscillator circuit itself.
It is important that the crystal load capacitance is speci-
fied correctly to “center” the tuning range. See Table 5.
A simple formula to obtain the “pulling” capability of a
crystal oscillator is:
where:
C
C
C
of the applied load capacitance presented by the
FS6128.
0 =
1 =
L1
and C
the shunt (or holder) capacitance of the crystal
the motional capacitance of the crystal
PIN
1
2
3
4
5
6
7
8
Functional Block Description
Oscillator (VCXO)
Voltage-Controlled Crystal
f
L2
(
= the two extremes (minimum and maximum)
ppm
)
TYPE
DO
DO
AO
AI
AI
P
P
P
2
C
1
C
0
C
XTUNE
C
NAME
XOUT
L
VDD
VDD
VSS
VSS
CLK
XIN
2
L
2
C
L
1
C
U
0
= Input with Internal Pull-Up; DI
10
VCXO Feedback
Power Supply (+3.3V)
VCXO Tune
Ground
Clock Output
Power Supply (+3.3V)
Ground
VCXO Drive
C
6
L
1
2
EXAMPLE: A crystal with the following parameters is
used: C
and maximum C
range (peak-to-peak) is:
3.2
The on-chip PLL is a standard frequency- and phase-
locked loop architecture. The PLL multiplies the reference
oscillator frequency to the desired output frequency by a
ratio of integers. The frequency multiplication is exact
with a zero synthesis error (unless otherwise specified).
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
1
Phase-Locked Loop (PLL)
f
= 0.025pF and C
DESCRIPTION
0
2
.
025
L1
6
= 10pF, and C
20
20
0
10
= 6pF. Using the minimum
6
10
10 6
L2
= 20pF, the tuning
300
ppm
.