ltc3612 Linear Technology Corporation, ltc3612 Datasheet - Page 20

• Manufacturer Part Number: ltc3612
• Description: 3a, 4mhz Monolithic Synchronous Step-down Dc/dc Converter
• Manufacturer: Linear Technology Corporation

LTC3612
APPLICATIONS INFORMATION
External Reference Input (DDR Mode)
If the DDR pin is tied to SV
is entered when V
down behavior is possible if the V
below 0.6V.
This allows TRACK/SS to be used as an external reference
between 0.3V and 0.6V if desired. During the run state in
DDR mode, the power good window moves in relation
to the actual TRACK/SS pin voltage if the voltage value
is between 0.3V and 0.6V. Note: if TRACK/SS voltage is
0.6V, either the tracking circuit or the internal reference
can be used.
During up/down tracking the output current foldback is
disabled and the PGOOD pin is always pulled down (see
Figure 8).
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the effi ciency and which change would produce
the most improvement. Effi ciency can be expressed as:
20
Effi ciency = 100% – (L1 + L2 + L3 + ...)
V
V
OUT2
OUT2
R4
R2
R1
R2
Figure 6b. Setup for Ratiometric Tracking
Figure 6a. Setup for Coincident Tracking
LTC3612 CHANNEL 2
LTC3612 CHANNEL 2
V
V
FB2
FB2
TRACK/SS2
TRACK/SS2
LTC3612
LTC3612
SLAVE
SLAVE
TRACK/SS
R4 ≤ R3
IN
R4
R2
R5
R6
V
exceeds 0.3V and tracking
V
OUT1
(DDR mode), the run state
OUT1
R3
R2
R3 R1/R2 < R5/R6
R4
LTC3612 CHANNEL 1
LTC3612 CHANNEL 1
V
V
FB1
FB1
TRACK/SS1
TRACK/SS
TRACK/SS1
LTC3612
MASTER
LTC3612
MASTER
voltage is
V
3612 F06b
IN
V
3612 F06a
IN
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V
quiescent current loss dominates the effi ciency loss at
very low load currents whereas the I
the effi ciency loss at medium to high load currents. In a
typical effi ciency plot, the effi ciency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The V
2. I
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from V
out of V
than the DC bias current. Both the DC bias and gate
charge losses are proportional to V
will be more pronounced at higher supply voltages.
internal switches, R
continuous mode the average output current fl owing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
(DC) as follows:
The R
be obtained from the Typical Performance Character-
istics curves. To obtain I
R
output current.
Other losses including C
losses and inductor core losses generally account for
less than 2% of the total loss.
2
L
R losses are calculated from the resistances of the
R
and multiply the result by the square of the average
SW
IN
DS(ON)
IN
quiescent current is due to two components: the
= (R
IN
to ground. The resulting dQ/dt is the current
IN
due to gate charge, and it is typically larger
DS(ON)TOP
quiescent current and I
for both the top and bottom MOSFETs can
SW
)(DC) + (R
, and external inductor, R
2
IN
R losses, simply add R
and C
DS(ON)
DS(ON)BOT
OUT
IN
2
and the duty cycle
2
; thus, their effects
R loss dominates
R losses. The V
ESR dissipative
)(1 – DC)
SW
L
. In
3612f
to
IN