ltc3730 Linear Technology Corporation, ltc3730 Datasheet - Page 14

• Manufacturer Part Number: ltc3730
• Description: 3-phase, 5-bit Intel Mobile Vid, 600khz, Synchronous Buck Controller
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC3730
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V
adjusted for different V
ratio of the application V
values. A way to estimate the C
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V
specified. C
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C
and C
parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
14
P
Main Switch Duty Cycle
Synchronous Switch Duty Cycle
P
SYNC
MAIN
V
OS
GS
are specified sometimes but definitions of these
=
=
C
MILLER
MILLER
V
V
⎡
⎢
⎢
⎣
V
a
V
IN
IN
OUT
V
MILLER EFFECT
IN
CC
2
–
V
= (Q
I
IN
MAX
Q
2
V
⎛
⎜
⎝
–
is the most important selection criteria
IN
N
OUT
B
U
I
1
MAX
V
– Q
N
TH IL
( )(
A
R
)/V
DS
( )
⎛
⎜
⎝
b
⎞
⎟
⎠
DR
Figure 5
DS
I
U
MAX
2
DS
voltages by multiplying by the
N
( )
+
1
=
C
+
to the curve specified V
V
DS
⎞
⎟
⎠
V
MILLER
TH IL
δ
2
MILLER
V
OUT
1
IN
( )
drain voltage, but can be
( )
1
R
W
+
DS ON
V
⎤
⎥
⎥
⎦
δ
=
+
GS
–
(
)
( )
term is to take the
V
f
•
⎛
⎜
⎝
R
V
)
DS ON
IN
+
(
–
V
+
IN
–
DS
U
V
)
V
OUT
3730 F05
DS
V
voltage
IN
⎞
⎟
⎠
RSS
DS
where N is the number of output stages, δ is the tempera-
ture dependency of R
resistance (approximately 2Ω at V
drain potential and the change in drain potential in the
particular application. V
typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. C
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
Both MOSFETs have I
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
high current efficiency generally improves with larger
MOSFETs, while for V
rapidly increase to the point that the use of a higher
R
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes, (D1 to D3 in Figure 1) conduct during
the dead time between the conduction of the two large
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
which could cost as much as several percent in efficiency.
A 2A to 8A Schottky is generally a good compromise for
both regions of operation due to the relatively small
average current. Larger diodes result in additional transi-
tion loss due to their larger junction capacitance.
C
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
A low ESR input capacitor sized for the maximum RMS
current must be used. The details of a close form equation
can be found in Application Note 77. Figure 6 shows the
input capacitor ripple current for different phase configu-
IN
DS(ON)
and C
device with lower C
OUT
Selection
2
DS(ON)
R losses while the topside N-channel
DS(ON)
IN
TH(IL)
> 12V, the transition losses
MILLER
, R
DR
is the data sheet specified
vs temperature curve, but
is the effective top driver
actually provides higher
GS
= V
MILLER
IN
), V
< 12V, the
OUT
IN
MILLER
is the
/V
3730fa
IN
.