mcm67b618bfn9 Freescale Semiconductor, Inc, mcm67b618bfn9 Datasheet - Page 2

• Manufacturer Part Number: mcm67b618bfn9
• Description: 64k X 18 Bit Burstram Synchronous Fast Static Ram With Burst Counter And Self-timed Write , Inc
• Manufacturer: Freescale Semiconductor, Inc

DQ9 – DQ17
DQ0 – DQ8
MCM67B618B
2
NOTE:
A0 – A15
UW
LW
ADSC
ADSP
G
All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-
formed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by asserting
ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid
data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address
is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
E
K
9
9
REGISTER
ADDRESS
REGISTER
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
NOTE: The burst wraps around to its initial state upon
WRITE
BURST SEQUENCE TABLE (See Note)
completion.
ADV
BLOCK DIAGRAM
REGISTER
ENABLE
A15 – A2
A15 – A2
A15 – A2
A15 – A2
CLR
16
(See Note)
A1 – A0
Q0
Q1
BURST LOGIC
A1
A1
A1
A1
A0
A1
2
A0
A0
A0
A0
A2 – A15
A0
A1
MOTOROLA FAST SRAM
INTERNAL
ADDRESS
9
16
REGISTERS
DATA–IN
18
9
MEMORY
64K x 18
ARRAY
OUTPUT
BUFFER
9
9