ltc1196-2bcs8-trpbf Linear Technology Corporation, ltc1196-2bcs8-trpbf Datasheet - Page 15

• Manufacturer Part Number: ltc1196-2bcs8-trpbf
• Description: 8-bit, So-8, 1msps Adcs With Auto-shutdown Options
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
Connection to a microprocessor or a DSP serial port is
quite simple (see Data Transfer section). It requires no
additional hardware, but the speed will be limited by the
clock rate of the microprocessor or the DSP which limits
the conversion time of the LTC1196/LTC1198.
Data Transfer
Data transfer differs slightly between the LTC1196 and the
LTC1198. The LTC1196 interfaces over 3 lines: CS, CLK
and D
in the LTC1196 Operating Sequence. After CS falls, the
fi rst CLK pulse enables D
conversion result is output on the D
high resets the LTC1196 for the next data exchange.
The LTC1198 can transfer data with 3 or 4 wires. The ad-
ditional input, D
confi guration.
The data transfer between the LTC1198 and the digital
systems can be broken into two sections: Input Data Word
and A/D Conversion Result. First, each bit of the input data
word is captured on the rising CLK edge by the LTC1198.
Second, each bit of the A/D conversion result on the D
line is updated on the rising CLK edge by the LTC1198. This
bit should be captured on the next rising CLK edge by the
digital systems (see A/D Conversion Result section).
Data transfer is initiated by a falling chip select (CS) signal
as shown in the LTC1198 Operating Sequence. After CS
falls the LTC1198 looks for a start bit. After the start bit
is received, the 4-bit input word is shifted into the D
input. The fi rst two bits of the input word confi gure the
LTC1198. The last two bits of the input word allow the
ADC to acquire the input voltage by 2.5 clocks before the
conversion starts. After the conversion starts, two null bits
and the conversion result are output on the D
ADDRESS IN
SHIFT MUX
CS
OUT
. A falling CS initiates data transfer as shown
D
IN1
2 NULL BITS
IN
, is used to select the 2-channel MUX
D
OUT1
SHIFT A/D CONVERSION
RESULT OUT
OUT
. After two null bits, the A/D
D
OUT
IN2
line. Bringing CS
D
OUT2
OUT
line. At
1196/98 AI01
OUT
IN
Start Bit
The fi rst “logical one” clocked into the D
goes low is the start bit. The start bit initiates the data
transfer. The LTC1198 will ignore all leading zeros which
precede this logical one. After the start bit is received,
the remaining bits of the input word will be clocked in.
Further inputs on the D
next CS cycle.
Multiplexer (MUX) Address
The 2 bits of the input word following the START bit assign
the MUX confi guration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table.
In single-ended mode, all input channels are measured
with respect to GND.
the end of the data exchange CS should be brought high.
This resets the LTC1198 in preparation for the next data
exchange.
Input Data Word
The LTC1196 requires no D
fi gured to have a single differential input. The conversion
result is output on the D
followed by zeros indefi nitely if clocks are continuously
applied with CS low.
The LTC1198 clocks data into the D
ing edge of the clock. The input data word is defi ned
as follows:
SINGLE-ENDED
DIFFERENTIAL
MUX MODE
MUX MODE
SGL/DIFF
START
MUX ADDRESS
1
1
0
0
LTC1198 Channel Selection
LTC1196/LTC1198
SGL/
DIFF
ODD/SIGN
ADDRESS
OUT
MUX
0
1
0
1
IN
ODD/
SIGN
IN
pin are then ignored until the
line in an MSB-fi rst sequence,
word. It is permanently con-
CHANNEL #
0
+
+
–
DUMMY
DUMMY
BITS
1
+
–
+
DUMMY
IN
119698 AI02
1196/98 AI03
input on the ris-
GND
IN
–
–
input after CS
15
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