isl6161 Intersil Corporation, isl6161 Datasheet - Page 6

• Manufacturer Part Number: isl6161
• Description: Dual Power Distribution Controller
• Manufacturer: Intersil Corporation

NOTE: Nominal CR Vth = Rilim x 10µA.
NOTE: Nominal time-out period in seconds = C
The ISL6161 responds to a load short (defined as a current
level 3X the OC set point with a fast transition) by
immediately driving the relevant N-Channel MOSFET gate to
0V in ~3µs. The gate voltage is then slowly ramped up soft
starting the N-Channel MOSFET to the programmed current
regulation limit level, this is the start of the time out period if
the abnormal load condition still exists. The programmed
current regulation level is held until either the OC event
passes or the time out period expires. If the former is the
case then the N-Channel MOSFET is fully enhanced and the
C
the time out period expires prior to OC resolution then both
gates are quickly pulled to 0V turning off both N-Channel
MOSFETs simultaneously.
Upon any UV condition the PGOOD signal will pull low when
tied high through a resistor to the logic supply. This pin is a
fault indicator but not the OC latch off indicator. For an OC
latch off indication, monitor CTIM, pin 10. This pin will rise
rapidly to 12V once the time out period expires. See block
diagram for OC latch off circuit suggestion.
The ISL6161 is reset by a rising edge on the ENABLE pin
and is turned on by the ENABLE pin being driven low.
ISL6161 Application Considerations
In a non PCI-Express, motor drive application Current loop
stabilization is facilitated through a small value resistor in
series with the gate timing capacitor. As the ISL6161 drives
a highly inductive current load, instability characterized by
the gate voltage repeatedly ramping up and down may
appear. A simple method to enhance stability is provided by
the substitution of a larger value gate resistor. Typically this
situation can be avoided by eliminating long point to point
wiring to the load.
PCI-EXPRESS
ADD-IN CARD
CONNECTOR
TIM
X4/X8
charging current is diverted away from the capacitor. If
X16
C
TIM
0.022µF
0.047µF
CAPACITOR
0.1µF
R
(kΩ)
4.99
4.99
ILIM
10
10
TABLE 1. (Continued)
3.3V R
NOMINAL
TABLE 2.
CR (A)
30, 3.3
15, 3.5
30, 3.3
15, 3.5
(mΩ),
SENSE
6
NOMINAL TIME OUT PERIOD
12V R
NOMINAL
CR (A)
40, 2.5
20, 2.6
16, 6.3
(mΩ),
8, 6.6
SENSE
TIM
4.4ms
9.4ms
20ms
x 200kΩ.
NOMINAL
CRVth
(mV)
100
100
53
53
ISL6161
With the ENABLE internal pull-up the ISL6161 is well suited
for implementation on either side of the connector where a
motherboard prebiased condition or a load board staggered
connection is present. In either case the ISL6161 turns on in
a soft start mode protecting the supply rail from sudden
current loading.
During the Time Out delay period with the ISL6161 in
current limit mode, the V
MOSFETs is reduced driving the N-Channel MOSFET
switch into a high r
out periods as the external N-Channel MOSFETs may be
damaged or destroyed due to excessive internal power
dissipation. Refer to the MOSFET manufacturers data sheet
for SOA information.
With the high levels of inrush current e.g., highly capacitive
loads and motor start up currents, choosing the current
regulation (CR) level is crucial to provide both protection
and still allow for this inrush current without latching off.
Consider this in addition to the time out delay when choosing
MOSFETs for your design.
Physical layout of Rsense resistors is critical to avoid
inadvertently lowering the CR and trip levels. Ideally trace
routing between the Rsense resistors and the ISL6161 is
direct and as short as possible with zero current in the sense
lines.
Open load detection can be accomplished by monitoring
the ISEN pins. Although gated off the external FET I
cause the ISEN pin to float above ground to some voltage
when there is no attached load. If this is not desired 5K
resistors from the xISEN pins to ground will prevent the
outputs from floating when the external switch FETs are
disabled and the outputs are open.
For PCI-Express applications the ISL6161 and the
ISL6118 provide the fundamental hotswap function for the
+12V & +3.3V main rails and the +3.3V aux respectively as
shown in Figure 13.
TO ISEN AND
CORRECT
R
ISET
FIGURE 1. SENSE RESISTOR PCB LAYOUT
DS(ON)
SENSE RESISTOR
GS
CURRENT
state. Thus avoid extended time
of the external N-Channel
INCORRECT
DSS
will