isl88550a Intersil Corporation, isl88550a Datasheet
isl88550a
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isl88550a Summary of contents
Page 1
... MOSFET. Once overcurrent is removed, the regulator is allowed to enter soft-start again. This helps minimize power dissipation during short-circuit condition. Additionally, overvoltage and undervoltage protection mechanisms are built in. The ISL88550A allow flexible sequencing and standby power management using SHDNA#, and STBY# inputs. Ordering Information ...
Page 2
... Pinout 2 ISL88550A ISL88550A (28 LD TQFN) TOP VIEW TON 1 OVP/UVP 2 REF 3 4 ILIM POK1 5 6 POK2 7 STBY LGATE 21 20 BOOT 19 PHASE 18 UGATE 17 VIN 16 OUT FN6168.2 October 1, 2007 ...
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... V Shutdown Supply DD DD Current AV Undervoltage Lockout Threshold DD REFERENCE Reference Voltage Reference Load Regulation REF Undervoltage Lockout 3 ISL88550A Thermal Information Thermal Resistance TQFN Package (Notes 1, 2 Operating Conditions + 0.3V DD Junction Temperature Range .-55°C to +150°C + 0.3V DD Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C + 0.3V DD Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -65°C + 150°C Pb-free reflow profile ...
Page 4
... State Dead Time (Additional to Adaptive Delay) INPUTS AND OUTPUTS Logic Input Threshold High (SHDNA#, SKIP#, STBY#) Logic Input Current (SHDNA#, SKIP#, STBY#) FB Input Logic Level Input Bias Current (FB) 4 ISL88550A = AV = SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V CONDITIONS UVP/OVP = AV DD ...
Page 5
... On-time and off-time specifications are measured from 50% point to 50% point at the UGATE pin with PHASE = GND, V capacitor connected from UGATE to PHASE. Actual in-circuit times may differ due to MOSFET switching speeds. 5 ISL88550A = AV = SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V, DD ...
Page 6
... This pin can range from 2V to 25V. 18 UGATE High-Side Gate-Driver Output. Swings from PHASE to BOOT. UGATE is low when in shutdown or UVLO. 6 ISL88550A On-Time Selection-Control Input. This four-level logic input sets the nominal UGATE on-time. Connect , or leave t unconnected to select the following nominal switching frequencies: DD ...
Page 7
... SKIP IN 80 25V - SKIP 0.001 0.010 0.100 LOAD (A) FIGURE 1. EFFICIENCY vs LOAD (1.8V ISL88550A FUNCTION for low-noise, forced-PWM mode. Connect to GND to DD and 12V 1.8V GND, SKIP DDQ ON unless otherwise noted. 700 600 500 3V - PWM ...
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... SKIP 12V - PWM SKIP PWM 0.001 0.010 0.100 LOAD (A) FIGURE 7. OUTPUT RIPPLE vs LOAD (1.8V ISL88550A V = 12V 1.8V GND, SKIP DDQ ON unless otherwise noted. (Continued) 590 570 550 530 510 490 470 450 FIGURE 4. SWITCHING FREQUENCY vs TEMPERATURE 1 ...
Page 9
... FIGURE 9. VTTR REGULATION vs VTTR LOAD I = 12A 15mA VDDQ VTTR 20µs/DIV FIGURE 11. LOAD TRANSIENT (VTT -1.5A TO 1.5A 5V 12A 1.5A VDDQ VTT VTTR 100µs/DIV FIGURE 13. POWER-DOWN WAVEFORMS 9 ISL88550A V = 12V 1.8V DDQ ON unless otherwise noted. (Continued) I VTT 10A 0A 0.01 0.02 0.03 0. VDDQ 100mV/DIV ...
Page 10
... VTT 2ms/DIV FIGURE 15. VDDQ START-UP AND SHUTDOWN INTO LIGHT LOAD, DISCHARGE ENABLED 50µs/DIV FIGURE 17. OVERVOLTAGE AND TURN-OFF OF BUCK OUTPUT UVP ENABLE 50µs/DIV FIGURE 19. SHORT CIRCUIT AND RECOVERY OF VDDQ 10 ISL88550A V = 12V 1.8V GND, SKIP DDQ ON unless otherwise noted. (Continued 1.5A, I ...
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... QUAD LEVEL OVP/UVP DECODER BUCK ON/OFF BLANK SHDNA# BIAS SHUTDOWN ON/OFF DECODER STBY# 0.7 x INTREF VTT ON/OFF VTTR ON/OFF INTREF+10% INTEREF-10% POK1 N FB INTREF/2 + 10% POK2 N INTEREF/2 - 10% 11 ISL88550A VIN t OFF TRIG ON TIME Q1-SHOT COMPUTE TRIG Q 1-SHOT 1. INTREF R OVP/UVP LATCH + 1.0V ...
Page 12
... Bias Supply (V and The ISL88550A requires an external +5V bias supply in addition to the input voltage (V ). Keeping the bias supply IN external to the IC improves the efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and the gate drivers ...
Page 13
... DC output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the ISL88550A regulates the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous ...
Page 14
... In forced-PWM mode, the ISL88550A also implements a negative current limit to prevent excessive reverse inductor currents when the Buck Regulator output is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when V is adjusted ...
Page 15
... Buck Regulator’s internal soft-start allows a gradual increase of the current limit level during start-up to reduce the input surge currents. The ISL88550A divides the soft-start period into five phases. During the first phase, the controller limits the current limit to only 20% of the full current limit. If the ...
Page 16
... V rise 10% above or 10% VTTS VTTR 16 ISL88550A below their nominal regulation voltage, the ISL88550A pulls POK2 low. For logic level output voltages, connect an power below external pull-up resistor between POK2 and AV DD resistor works well in most applications. Note that the POK2 . A 100kΩ ...
Page 17
... PFM/PWM switchover occurs. Setting the Output Voltage (Buck) Preset Output Voltages The ISL88550A allows the selection of common voltages without requiring external components (Figure 25). Connect FB to GND for a fixed 2.5V output, or connect FB directly to OUT for a fixed 0.7V output. ...
Page 18
... FIGURE 25. DUAL-MODE FEEDBACK DECODER Setting the Buck Regulator Output (V Resistive Voltage-Divider at FB The Buck Regulator output voltage can be adjusted from 0.7V to 3.5V using a resistive voltage-divider (Figure 26). The ISL88550A regulates fixed reference voltage (0.7V). The adjusted output voltage is shown in Equation 6: ⎛ ⎞ ⎜ ...
Page 19
... OSCON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. If the ISL88550A are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than +10° ...
Page 20
... I GATE UGATE GATE 20 ISL88550A where RUGATE is the high-side MOSFET driver’s ON-resistance (1.5Ω typical) and RGATE is the internal gate resistance of the MOSFET (~2Ω): = P HSDR where V Equation 22, allow about 20% more for additional losses ; for IN(MAX) because of MOSFET output capacitances and low-side ...
Page 21
... Setting the Current Limit (Buck) The current-sense method used in the ISL88550A makes use of the ON-resistance ( the low side MOSFET DS(ON "Typical Application Circuit" on page 22). When 2 calculating the current limit, use the worst-case maximum value for r from the MOSFET data sheet, and add ...
Page 22
... Low OUT The overshoot during a full-load to no-load transient due to stored inductor energy can be calculated using Equation 34: V SOAR (EQ. 33) ⎤ ) ⎥ ⎦ ISL88550A OVP/UVP OVP/UVP VDD VDD ISL88550A VIN VIN BOOT BOOT UGATE UGATE 0.22µF PHASE ...
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... V equation in “Design SAG Procedure” on page 17). The absolute point of dropout is when the inductor current ramps down during the minimum off-time ( ramps up during the on-time ( ISL88550A ISL88550A AVDD OVP/UVP SS VDD TON VIN SKIP# BOOT Q1 Q1 ...
Page 24
... PGND2 pin. The REFIN pin (pin 14) should be separately routed with a clean trace and adequately bypass to AGND. A suggested layout of the board can be found in the Evaluation Board Kit of ISL88550A. ). SENSE FN6168.2 October 1, 2007 ...
Page 25
... CORNER REF. OPTION 4X BOTTOM VIEW SECTION "C-C" TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE 25 ISL88550A L28.5x5B 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WHHD-1 ISSUE I) SYMBOL 0. E 0. ...