isl8540 Intersil Corporation, isl8540 Datasheet - Page 14

• Manufacturer Part Number: isl8540
• Description: Dc/dc Power Switching Regulator
• Manufacturer: Intersil Corporation

the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ΔV
incorporates a feed forward loop that accounts for changes
in the input voltage. This maintains a constant modulator
gain.
Modulator Break Frequency Equations
The compensation network consists of the transconductance
amplifier (internal to the ISL8540) and the impedance
networks Z
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f
margin. Phase margin is the difference between the closed
loop phase at f
section relate the compensation network’s poles, zeros and
gain to the components (R
Figure 28. Use these guidelines for locating the poles and
zeros of the compensation network:
1. Pick Gain (R
3. Place 2
4. Place 1
f LC
2. Place 1
ΔV
FIGURE 28. VOLTAGE-MODE BUCK CONVERTER
OSC
bandwidth.
=
------------------------------------------ -
2π x
OSC
IN
ST
ND
ST
L O x C O
COMPARATOR
1
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
and Z
Zero Below Filter’s Double Pole (~75% f
Pole at the ESR Zero.
0dB
Zero at Filter’s Double Pole.
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
C
V
ISL8540
3
E/A
10
PWM
gm/(R
and 180°. The equations in the following
V
FB
Z
+
-
OUT
FB
-
+
COMP
. The goal of the compensation
C
REFERENCE
2
6
REFERENCE
+R
g
=
2
m
, R
-
+
1.20
3
14
) for desired converter
DRIVER
DRIVER
R
f ESR
3
Z
4
, R
IN
×
0dB
OSC
4
⎛
⎜
⎝
=
1
, R
FB
+
Z
------------------------------------------- -
2π x ESR x C O
) and adequate phase
FB
6
R
------ -
R
. The ISL8540
, C
LX
2
3
R
(PARASITIC)
⎞
⎟
⎠
V
D
C
3
IN
10
7
IN
Z
R
1
) divided by the
, C
IN
2
L
R
ESR
6
O
6
C
, and C
O
V
OUT
(EQ. 11)
LC
V
).
OUT
7
) in
ISL8540
Compensation Break Frequency
Equations
Assumption: R6<<R2, R6<<R3, and C10<<C6.
Figure 29 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 29. Using the guidelines on page 13 should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation gain.
Check the compensation gain at f
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 29 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
A more detailed explanation of voltage mode control of a
buck regulator can be found in Tech Brief TB417, titled
“Designing Stable Compensation Networks for Single Phase
Voltage Mode Buck Regulators.”
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently
f
f
FIGURE 29. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
5. Place 2
6. Check Gain against Error transconductance’s Open-
7. Estimate Phase Margin - Repeat if Necessary.
Z1
Z2
FB
100
-20
-40
-60
80
60
40
20
Loop Gain.
=
=
0
and Z
--------------------------------------------------------- -
2π
-------------------------- -
2πR
10
(R
20LOG
⋅
MODULATOR
4
IN
(
--------------------------------- - C
1
2
/R
R
ND
⋅
2
4
to provide a stable, high bandwidth (BW) overall
C
GAIN
)
100
⋅
7
g
Pole at Half the Switching Frequency.
g
1
m
m
+
1
)
1k
F
⋅
Z1
F
FREQUENCY (Hz)
6
LC
F
Z2
10k
f
f
P1
P2
F
F
P1
ESR
P2
(V
=
=
IN
100k
20LOG
-------------------------- -
2πR
-----------------------------
2πR
with the capabilities of
F
/ΔV
P2
OSC
1
6
4
1
OPEN LOOP
ERROR AMP GAIN
⋅
⋅
C
C
1M
)
7
10
COMPENSATION
September 18, 2007
CLOSED LOOP
10M
GAIN
GAIN
(EQ. 12)
FN6495.4