st7033 Sitronix Technology Corporation, st7033 Datasheet - Page 8

• Manufacturer Part Number: st7033
• Description: 4 X 96 Dot Matrix Lcd Controller/driver
• Manufacturer: Sitronix Technology Corporation

ST7033
LCD DRIVER SUPPLY
POWER SUPPLY
Configuration Pins
Ver 1.0
XV0I, XV0O, XV0S
VGI, VGO, VGS
V0I, V0O, V0S;
D0…D7
MODE
E_RD
VDD1
VDD2
OSC
VRS
VSS
VM
CP
Supply
Supply
Supply
Power
Power
Power
Power
Power
Power
Power
I
I
I
I
I
Read/Write operation control pin (if using Parallel interface).
Data Bus. If /CSB signal is not actived, D7…D0 are high impedance.
Ground.
Digital circuits supply voltage.
The 2 power supply rails, VDD1 and VDD2, could be connected together.
Use this power to be the high voltage level for the Option pins.
Analog circuits supply voltage.
The 2 power supply rails, VDD and VDD2, could be connected together.
Negative LCD driver supply voltages.
XV0I, XV0O & XV0S should be separated in ITO layout.
XV0I, XV0O & XV0S should be connected together in FPC layout.
This is a multi-level power supply for the liquid crystal.
V0
V0I, V0O & V0S should be separated in ITO layout.
V0I, V0O & V0S should be connected together in FPC layout.
VGI, VGO & VGS should be separated in ITO layout.
VGI, VGO & VGS should be connected together in FPC layout.
LCD driving voltage for commons.
Reserved to monitor internal Voltage Regulator reference level, must be left
open.
Test pin.
Must fix to “L”
Set Booster stage.
VSS=4X;
VDD=5X.
6800-series
8080-series
MPU Type
VG
Parallel interface (6800 or 8080):
I/O port which is connected to the standard 8-bit MPU data bus.
Serial SPI interface (3 line or 4 line):
SCLK: D0;
SDA: D1~D3;
D4~D7 must connect to VDD1.
OSC=”H”: Use the built-in oscillator.
OSC=”L”: Both external clock and built-in oscillator are inhibited. And
the display circuits will not be clocked and kept in a DC state. To
avoid this, the chip should always be put into Power-Down Mode
before stopping the clock.
If using external clock, connect this pin to the external clock.
VM
VSS
E_RD
/RD
E
XV0
8/39
Signals (Instruction or Data) on
data bus will be latched by MPU
or this IC (depends on R/W) at
the falling edge of this signal.
Internal status (or display data)
will be read out to data bus after
the falling edge of this signal.
Interface Mode
2008/05/29
1
8
1
5
4
4
7
6
3
1
1
1