st20-gp1 STMicroelectronics, st20-gp1 Datasheet
st20-gp1
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st20-gp1 Summary of contents
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... Real time Serial communications clock/calendar 2 UART (ASC) 1 OS-Link 4K SRAM Parallel input/output Programmable memory Byte-wide interface parallel port ROM/ RAM FLASH APPLICATIONS Global Positioning System (GPS) receivers Car navigation systems Fleet management systems Time reference for telecom systems ST20-GP1 . . . 1/116 42 1672 02 ...
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... Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 ST20-GP1 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 DSP module registers .......................................................................................................................... 13 4 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 Registers .............................................................................................................................................. 18 4.2 Processes and concurrency ................................................................................................................ 19 4.3 Priority .................................................................................................................................................. 21 4.4 Process communications ..................................................................................................................... 21 4.5 Timers .................................................................................................................................................. 22 4.6 Traps and exceptions .......................................................................................................................... 23 5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 Interrupt vector table ............................................................................................................................ 29 5.2 Interrupt handlers ................................................................................................................................. 29 5.3 Interrupt latency ................................................................................................................................... 30 5.4 Pre-emption and interrupt priority ........................................................................................................ 30 5 ...
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... Parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.1 PIO Port ............................................................................................................................................... 85 15 Byte-wide parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 15.1 EMI mode operation ............................................................................................................................ 88 15.2 Parallel link (DMA) mode operation ..................................................................................................... 88 15.3 Configuration registers ......................................................................................................................... 88 15.4 External data transfer protocols ........................................................................................................... 89 16 Configuration register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 17 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 18 GPS Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 18.1 Accuracy ............................................................................................................................................ 100 18.2 Time to first fix ................................................................................................................................... 101 ST20-GP1 3/116 ...
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... Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.1 EMI timings ........................................................................................................................................ 102 19.2 Link timings ........................................................................................................................................ 104 19.3 Reset and Analyse timings ................................................................................................................ 105 19.4 ClockIn timings .................................................................................................................................. 106 19.5 Parallel port timings ........................................................................................................................... 107 20 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 21 Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 21.1 ST20-GP1 package pinout ................................................................................................................ 112 21.2 100 pin PQFP package dimensions .................................................................................................. 113 22 Device 115 23 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4/116 ...
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... No TCXO The ST20-GP1 supports large values of frequency offset, allowing the use of a very low cost oscillator, thus saving the cost of a Temperature Controlled Crystal Oscillator (TCXO). The CPU and software have access to the part-processed signal to enable accelerated acquisition time. ...
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... I/O • Interrupt controller • Real time clock/calendar • Watchdog timer The ST20-GP1 is supported by a range of software and hardware development tools for PC and UNIX hosts including an ANSI-C ST20 software toolset and the ST20 INQUEST window based debugging toolkit. 6/116 ...
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... CPU The Central Processing Unit (CPU) on the ST20-GP1 is the ST20 32-bit processor core. It contains instruction processing logic, instruction and data pointers, and an operand register. It directly accesses the high speed on-chip memory, which can store data or programs. The processor can access Mbytes of memory via the programmable memory interface ...
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... GPS hardware DSP Interrupt Interrupts controller Low power controller Real time clock 4K SRAM Programmable memory interface RAM Figure 2.1 ST20-GP1 architectural block diagram 8/116 ST20 Serial communications 2 UART 1 OS-Link Parallel input/output Byte-wide parallel System services ROM/ FLASH ST20-GP1 CPU OS-Link ...
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... SRAM and a programmable memory interface. The programmable memory interface is also referred external memory interface (EMI). The ST20-GP1 uses 8 or 16-bit external RAM 16-bit ROM, and supports an address width of 20 bits. The ST20-GP1 product has 4 Kbytes of on-chip SRAM. The advantage of this is the ability to store time critical code on chip, for instance interrupt routines, software kernels or device drivers, and even frequently used data ...
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... The UARTs provide an asynchronous serial interface and can be programmed to support a range of baud rates and data formats, for example, data size, stop bits and parity. There is one OS-Link on the ST20-GP1 which acts as a DMA engine independent of the CPU. The OS-Link uses an asynchronous bit-serial (byte-stream) protocol, each bit received is sampled five times, hence the term oversampled link (OS-Link) ...
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... Digital signal processing module The ST20-GP1 chip includes 12 channel GPS correlation DSP hardware designed to handle twelve satellites, two of which can be initialized to support the RTCA-SC159 specification. The digital signal processing (DSP) module extracts GPS data from the incoming IF (Intermediate Frequency) data. There are a number of stages of processing involved; these are summarized below and in Figure 3 ...
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... ST20-GP1 as doppler shift, crystal accuracy, etc.). The sum frequency (~8 MHz) is removed by low-pass filtering in the correlator. This stage is common to all 12 channels. Correlation against pseudo-random sequence The GPS data is transmitted as a spread-spectrum signal (with a bandwidth of about 2 MHz). In order to recover the data it is necessary to correlate against the same Pseudo-Random Noise (PRN) signal that was used to transmit the data ...
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... Absent 16-bit values padded with #8000 header sample sync rate 3.1 DSP module registers The GPS hardware channels of the ST20-GP1 are controlled by three sets of registers: 1 DSPControl register 2 PRNcode0-11 and PRNphase0-11 registers 3 NCOfrequency0-11 and NCOphase0-11 registers The base addresses for the DSP registers are given in the Memory Map chapter. ...
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... ST20-GP1 DSPControl DSP base address + #140 Bit Bit field Function 1:0 SampleRate These bits control the sampling rate (the rate at which data is sent to the DMA controller). The encoding of these bits is as follows: 2 NCOResetEnable When set to 1, the accumulated NCO phase for a channel is reset when the corre- sponding PRN code register is written ...
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... ST20-GP1 a by bits 15/116 ...
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... ST20-GP1 The 19-bit value comprises three fields. The 3 least significant bits represent the fractional-delay in eighths of a code-chip. The middle 10 bits represent the integer delay in code-chips, 0-1022, with the value 1023 illegal. The upper 6 most significant bits represent the delay in integer milliseconds. ...
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... If uninitialized by the software, this register defaults to 11 1111 1111 (#3FF) as required for GPS satellites. PRNinitialVal0-1 DSP base address + #100, #104 Bit Bit field Function 9:0 InitialValue Initial value of the RTCA-SC159 satellite channel. Table 3.8 PRNinitialVal0-1 register format ST20-GP1 Write only Write only 17/116 ...
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... ST20-GP1 4 Central processing unit The Central Processing Unit (CPU) is the ST20 32-bit processor core. It contains instruction processing logic, instruction and data pointers, and an operand register. It can directly access the high speed on-chip memory, which can store data or programs. Where larger amounts of memory are required, the processor can access memory via the External Memory Interface (EMI) ...
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... In the linked process list shown in Figure 4.2, process S is executing and and R are active, awaiting execution. Only the low priority process queue registers are shown; the high priority process ones behave in a similar manner. ST20-GP1 19/116 ...
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... ST20-GP1 Registers FptrReg1 BptrReg1 Areg Breg Creg Wptr IptrReg Function Pointer to front of active process list Pointer to back of active process list Table 4.1 Priority queue control registers Each process runs until it has completed its action or is descheduled. In order for several processes to operate in parallel, a low priority process is only permitted to execute for a maximum of two timeslice periods ...
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... Communication between processes takes place over channels, and is implemented in hardware. Communication is point-to-point, synchronized and unbuffered result, a channel needs no process queue, no message queue and no message buffer. A channel between two processes executing on the same CPU is implemented by a single word in memory; a channel between processes executing on different processors is implemented by point- ST20-GP1 21/116 ...
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... ST20-GP1 to-point links. The processor provides a number of operations to support message passing, the most important being in (input message) and out (output message). The in and out instructions use the address of the channel to determine whether the channel is internal or external. This means that the same instruction sequence can be used for both hard and soft channels, allowing a process to be written and compiled without knowledge of where its channels are implemented ...
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... The trap handler is not re-entrant and must not cause a trap itself within the same group. All traps are individually maskable. 4.6.1 Trap groups The trap mechanism is arranged on a per priority basis. For each priority there is a handler for each group of traps, as shown in Figure 4.4. Workspaces 5 comparator 21 Alarm 21 Empty 31 Figure 4.3 Timer registers ST20-GP1 Program 23/116 ...
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... ST20-GP1 Low priority traps CPU Error trap handler Breakpoint System operations trap handler trap handler There are four groups of traps, as detailed below. • Breakpoint This group consists of the Breakpoint trap. The breakpoint instruction ( j0 ) calls the break- point routine via the trap mechanism. ...
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... Scheduler trap from runp (run process) or startp (start process). Scheduler trap from signal . 3 3 Start executing a process at a new priority level. 3 Caused by no process active at a priority level. Any, Signals that the causeerror instruction set the trap flag. encoded 0-3 ST20-GP1 25/116 ...
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... ST20-GP1 4.6.3 Trap handlers For each trap handler there is a trap handler structure and a trapped process structure. Both the trap handler structure and the trapped process structure are in memory and can be accessed via instructions, see Section 4.6.4. The trap handler structure specifies what should happen when a trap condition is present, see Table 4 ...
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... ST20-GP1 27/116 ...
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... GPS operation. Increasing pre-emption Interrupts on the ST20-GP1 are implemented via an on-chip interrupt controller peripheral. An interrupt can be signalled to the controller by one of the following: • a signal on an external Interrupt pin • ...
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... The value HandlerWptr, which is stored in the interrupt controller, points to the top of this Interrupting high priority process Wptr Handler Iptr Handler Status Creg Breg Areg Iptr Wptr Status Figure 5.2 State of interrupted process ST20-GP1 Interrupting low priority process or CPU idle Wptr Handler Iptr Handler Status Null Status 29/116 ...
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... ST20-GP1 workspace. The values of Iptr and Status to be used by the interrupt handler are loaded from this workspace and starts executing the handler. The value of Wptr is then set to the bottom of this save area. When an interrupt occurs when the CPU was idle or running at low priority, the Status is saved. ...
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... High level - triggered while input high 010 Low level - triggered while input low 011 Rising edge - low to high transition 100 Falling edge - high to low transition 101 Any edge - triggered on rising and falling edges 110 No trigger mode 111 No trigger mode ST20-GP1 Read/Write Read/Write 31/116 ...
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... ST20-GP1 On start-up, the Mask register is initialized to zero’s, thus all interrupts are disabled, both globally and individually. When written to the GlobalEnable bit, the individual interrupt bits are still disabled and must also have a 1 individually written to the InterruptEnable bit to enable the respective interrupt ...
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... Clear_Exec (address ‘interrupt base address + #108’) allows bits to be cleared individually. Writing a ‘1’ in this register resets the corresponding bit in the Exec register, a ‘0’ leaves the bit unchanged. Table 5.4 Pending register format Table 5.5 Exec register format ST20-GP1 Read/Write Read/Write 33/116 ...
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... ST20-GP1 6 Instruction set This chapter provides information on the instruction set. It contains tables listing all the instructions, and where applicable provides details of the number of processor cycles taken by an instruction. The instruction set has been designed for simple and efficient compilation of high-level languages. ...
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... Interruptible instruction A Instruction can be aborted and later restarted. D Instruction can deschedule T Instruction can timeslice Function code # #987 # -31 ( ldc #FFFFFFE1 Table 6.1 Prefix coding Table 6.2 Instruction features ST20-GP1 Memory code #43 #23 #45 #29 #28 #47 #61 #41 35/116 ...
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... ST20-GP1 6.3 Instruction set tables Function Memory Mnemonic code code ldlp 2 2X pfi ldnl 4 4X ldc 5 5X ldnlp 6 6X nfi ldl 8 8X adc 9 9X call ajw C CX eqc D DX stl E EX stnl F FX opr Memory Mnemonic ...
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... ST20-GP1 Notes 37/116 ...
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... ST20-GP1 Memory Mnemonic code 21F6 ladd 23F8 lsub 23F7 lsum 24FF ldiff 23F1 lmul 21FA ldiv 23F6 lshl 23F5 lshr 21F9 norm 26F4 slmul 26F5 sulmul Table 6.6 Long arithmetic operation codes Memory Mnemonic code F0 rev 23FA xword 25F6 cword 21FD xdble ...
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... Table 6.9 Timer handling operation codes Name byte subscript word subscript form double word subscript byte count word count load byte store byte move message Name load timer timer input timer alt start timer alt wait enable timer disable timer ST20-GP1 Notes I Notes 39/116 ...
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... ST20-GP1 Memory Mnemonic code out FF outword FE outbyte 24F3 alt 24F4 altwt 24F5 altend 24F9 enbs 23F0 diss 21F2 resetch 24F8 enbc 22FF disc Table 6.10 Input and output operation codes Memory Mnemonic code 22F0 ret 21FB ldpi 23FC gajw F6 gcall 22F1 ...
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... Name 1 initialize data for 2D block move 2D block copy 2D block copy non-zero bytes 2D block copy zero bytes Name calculate crc on word calculate crc on byte count bits set in word reverse bits in word reverse bottom n bits in word ST20-GP1 Notes Notes Notes A A ...
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... ST20-GP1 Memory Mnemonic code 27F3 cflerr 29FC fptesterr 26F3 unpacksn 26FD roundsn 26FC postnormsn 27F1 ldinf Table 6.16 Floating point support operation codes Memory Mnemonic code 2CF7 cir 2CFC ciru 2BFA cb 2BFB cbu 2FFA cs 2FFB csu 2FF8 xsword 2BF8 xbword Table 6.17 Range checking and conversion instructions ...
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... ST20-GP1 Notes Notes D Notes A A ...
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... ST20-GP1 Memory Mnemonic code 26FE ldtraph 2CF6 ldtrapped 2CFB sttrapped 26FF sttraph 60F7 trapenb 60F6 trapdis 60FB tret Memory Mnemonic code 68FC ldprodid 63F0 nop Table 6.23 Processor initialization and no operation instructions Memory Mnemonic code 64FF clockenb 64FE clockdis 64FD ldclock 64FC ...
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... System memory use The ST20-GP1 has a signed address space where the address ranges from MinInt (#80000000) at the bottom to MaxInt (#7FFFFFFF) at the top. The ST20-GP1 has an area of 4 Kbytes of RAM at the bottom of the address space provided by on chip memory. The bottom of this area is used to store various items of system state ...
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... ST20-GP1 7.2 Boot ROM When the processor boots from ROM, it jumps to a boot program held in ROM with an entry point 2 bytes from the top of memory at #7FFFFFFE. These 2 bytes are used to encode a negative jump 256 bytes down in the ROM program. For large ROM programs it may then be necessary to encode a longer negative jump to reach the start of the routine ...
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... Figure 7.1 ST20-GP1 memory map USE User code/Data/Stack and Boot ROM RESERVED DSP controller peripheral (registers accessed via CPU device accesses) Parallel port controller peripheral (registers accessed via CPU device accesses) PIO controller peripheral ...
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... High priority Breakpoint trapped process High priority Breakpoint trap handler RESERVED Byte wide parallel port input DMA channel DSP module DMA channel Link0 (boot) input channel RESERVED Byte wide parallel port output DMA channel RESERVED Link0 output channel Figure 7.1 ST20-GP1 memory map MEMORY BANK Bank 0 ...
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... MinInt (#80000000) extending upwards, as shown in Figure 8.1. This memory can be used to store on-chip data, stack or code for time critical routines. Where internal memory overlays external memory, internal memory is accessed in preference. External memory #80001000 SRAM MinInt #80000000 Figure 8.1 SRAM mapping ST20-GP1 49/116 ...
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... Programmable memory interface The ST20-GP1 programmable memory interface provides glueless support for up to four banks of SRAM or ROM memory. Sufficient configuration options are provided to enable the interface to be used with a wide variety of SRAM speeds, permitting systems to be built with optimum price/ performance trade-offs. Although designed primarily for SRAM-like memory devices, the confi ...
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... MemAddr1-19 External address bus. The ST20-GP1 uses 30 bits of addressing internally but only the bottom 18 bits are brought out to external pins (MemAddr2-19); MemAddr1 is generated by the EMI. MemAddr1-19 is valid and constant for the whole duration of an external access. The memory locations in each bank can be accessed at multiple addresses, as bits 20-29 are ignored when making external accesses ...
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... ST20-GP1 the initial bus width of all banks after reset. BootSource[1:0] Bootstrap start-up conditions 00 Boot from link. 16-bit bus width for all banks. 01 Boot from ROM. 8-bit bus width for all banks. Link operational. 10 Boot from ROM. 16-bit bus width for all banks. Link powered down. ...
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... OEe1 time notMemOE MemData0-7 MemData8-15† * Only when bus width is 8-bit. Inactive when bus width is 16-bit. † Ignored when bus width is 8-bit. Figure 9.2 Configuration parameters for a read access Access duration CEe2 time Read data latched ST20-GP1 BusRelease time on chip 53/116 ...
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... ST20-GP1 Figure 9.3 shows the generic EMI activity during a write access. notMemOE is inactive during a write access, and the function of notMemWB1 is dictated by the bus width of the bank in the same way as for a read access. MemData8-15 is held in high impedance during a write access if the bus width is 8-bit, otherwise it follows the timing configured for MemData0-7. ...
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... ST20-GP1 notMemWB0 ...
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... ST20-GP1 in the following two cases: • The previous access was a read and the pending one is a write. The write access will not start until the programmed number of BusReleaseTime cycles have elapsed. • The previous access was to a different bank to the pending access (bank switch). One cycle is always inserted between accesses to different banks. Note that, if the fi ...
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... Note, the clock shown in the figures is the internal on-chip clock and is provided as a guide to show the minimum setup time of MemWait relative to the strobes. clock MemWait Strobe1 Strobe2 Strobe3 Figure 9.5 Strobe activity without MemWait clock MemWait Strobe1 Strobe2 Strobe3 Figure 9.6 Strobe activity with MemWait MemWait wait asserted cycle ST20-GP1 57/116 ...
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... The EMIConfigLock register is provided to write protect the EMIConfigData0-3 registers (further writes to these registers are ignored). This bit is set by performing a devsw instruction to the given address; the write data is ignored. This register, once set, can only be cleared by resetting the ST20-GP1. EMIConfigLock EMI base address + #10 Bit Bit fi ...
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... Table 9.8 EMI signal values during reset Table 9.9 shows the configuration values for all banks during and after reset. If the BootSource0-1 pins indicate that the ST20-GP1 will boot from ROM, the BusWidth is set to the correct value as the ST20-GP1 comes out of reset. ...
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... When booting from ROM, the first EMI access will be an instruction fetch from bank 3. When booting from a link, the bootstrap is loaded into the ST20-GP1 internal SRAM located logically at the bottom of bank 0. The default bus width for all banks is set at reset by reading the value on the BootSource0-1 pins (see Table 9.1). If this bus width is inappropriate for a particular bank, then confi ...
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... Low power control The ST20-GP1 is designed for 0.5 micron, 3.3V CMOS technology and runs at speeds 32.736 MHz. 3.3V operation provides reduced power consumption internally and allows the use of low power peripherals. In addition, to further enhance the potential for battery operation, a low power power-down mode is available. ...
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... When the counter has counted down to zero, assuming no other valid wake-up sources occur first, the ST20-GP1 exits low power mode and the global clocks are turned back on. Whilst the clocks are turned off the LowPowerStatus pin is high, otherwise it is low. ...
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... When the low power alarm counts down to the value #1, the notWdReset pin is asserted low for 1 low power clock cycle. In addition an internal reset of the ST20-GP1 is performed. 10.3 Low power configuration registers The low power controller is allocated a 4k block of memory in the internal peripheral address space ...
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... ST20-GP1 LPAlarmLS and LPAlarmMS The LPAlarmLS and LPAlarmMS registers are the least significant word and most significant word of the LPAlarm register. This is used to program the low power alarm. LPAlarmLS LPC base address + #410 Bit Bit field Function 31:0 LPAlarmLS Least significant word of the low power alarm. ...
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... TimesOneMode 2 x1 16.368 MHz 4 x2 32.736 MHz 6 x3 RESERVED Table 10.9 SysRatio register format 0 alarm 1 watchdog 0 set external notRST 1 set to 1 when the watchdog counter is #1 and the WdEnable register is 1 Table 10.11 WdFlag register format ST20-GP1 Read Read/Write Read 65/116 ...
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... ST20-GP1 LPClockIn 10 pF GND A - this node should have very low capacitance < this node must have zero dc load. Figure 10.1 Watch crystal clocking source 66/116 LPClockOsc A B 330 K watch crystal 22 pF (32768 Hz) GND internal low power clock ...
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... If CPUAnalyse is taken high when the ST20-GP1 is running, the ST20-GP1 will halt at the next descheduling point. CPUReset may then be asserted. When CPUReset comes low again the ST20-GP1 will be in its reset state, and information on the state of the machine when it was halted by the assertion of CPUAnalyse, is maintained permitting analysis of the halted machine. ...
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... ROM. 11.2.2 Booting from link When booting from a link, the ST20-GP1 will wait for the first bootstrap message to arrive on the link. The first byte received down the link is the control byte. If the control byte is greater than 1 (i.e. ...
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... Following a peek or poke , the ST20-GP1 returns to its previously held state. Any number of accesses may be made in this way until the control byte is greater than 1, when the ST20-GP1 will commence reading its bootstrap program. 0 ...
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... ST20-GP1 12 Serial link interface (OS-Link) The OS-Link based serial communications subsystem provides serial data transfer. Its main function is for booting the device during software development. The OS-Link is a serial communications engine consisting of two signal wires, one in each direction. OS-Links use an asynchronous bit-serial (byte-stream) protocol, each bit received is sampled fi ...
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... OSLinkOut OSLinkIn Figure 12.2 OS-Links directly connected OSLinkOut OSLinkIn Figure 12.3 OS-Links connected by transmission line OSLinkOut OSLinkIn Figure 12.4 OS-Links connected by buffers OSLinkIn OSLinkOut OSLinkIn RM Zo=100 ohms OSLinkOut RM Zo=100 ohms OSLinkIn buffers OSLinkOut ST20-GP1 71/116 ...
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... ST20-GP1 13 UART interface (ASC) The UART interface, also referred to as the Asynchronous Serial Controller (ASC), provides serial communication between the ST20 device and other microcontrollers, microprocessors or external peripherals. The ASC supports full-duplex asynchronous communication, where both the transmitter and the receiver use the same data frame format and the same baud rate. Data is transmitted on the transmit data output pin (TXD) and received on the receive data input pin (RXD) ...
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... An odd parity bit will be cleared in this case. The parity error flag (ParityError) will be set if a wrong parity bit is received. The parity bit itself will be stored in bit 7 of the ASCRxBuffer register. ST20-GP1 73/116 ...
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... ST20-GP1 start D0 D1 bit (LSB) 9-bit data frames 9-bit data frames consist of: • nine data bits D0-8; • eight data bits D0-7 plus an automatically generated parity bit; • eight data bits D0-7 plus a wake-up bit. Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An even parity bit will be set, if the modulo-2-sum of the eight data bits is 1 ...
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... For 1 and 2 stop bits, the majority decision of the seventh, eighth, and ninth samples during the stop bits is used to determine the effective stop bit values Figure 13.3 9-bit data frames ST20-GP1 2nd 1st D7 9th stop stop bit bit ...
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... ST20-GP1 For 1.5 stop bits, the majority decision of the fifteenth, sixteenth, and seventeenth samples during the stop bits is used to determine the effective stop bit value. When the last stop bit has been received (at the end of the last programmed stop bit period) the content of the receive shift register is transferred to the receive data buffer register (ASCRxBuffer) ...
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... SysRatio register, see section 10.3, in calculating the CPU frequency. The table below lists various commonly used baud rates together with the required reload values and the deviation errors for the ST20-GP1 using a CPU clock of 33.736 MHz. Baud rate Reload value ...
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... ST20-GP1 An overall interrupt request signal (ASC_interrupt) is generated from the OR of the ErrorInterrupt signal and the TxEmpty, TxBufEmpty and RxBufFull signals. Note: the status register cannot be written directly by software. The reset mechanism for the status register is described below. The transmitter interrupt status bits (TxEmpty, TxBufEmpty) are reset when a character is written to the transmitter buffer ...
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... ASCBaudRate register is performed, the timer will not be reloaded until the first CPU clock cycle after the Run bit is 1. TxEmpty TxEmpty TxBufEmpty TxBufEmpty RxBufFull RxBufFull Figure 13.5 ASC interrupt generation ST20-GP1 TxEmpty Idle RxBufFull 79/116 ...
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... ST20-GP1 ASCBaudRate ASC base address + #00 Bit Bit field Write Function 15:0 ReloadVal 16-bit reload value Table 13.2 ASCBaudRate register format ASCTxBuffer register Writing to the transmit buffer register starts data transmission. ASCTxBuffer ASC base address + #04 Bit Bit field Function 0 TD0 Transmit buffer data D0 1 TD1 ...
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... Note: Serial data transmission or reception is only possible when the baud rate generator run bit (Run) is set to 1. When the Run bit is set to 0, TXD will be 1. Setting the Run bit to 0 will immediately freeze the state of the transmitter and receiver. This should only be done when the ASC is idle. ST20-GP1 Read only 81/116 ...
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... ST20-GP1 ASCControl ASC base address + #0C Bit Bit field Function 2:0 Mode ASC mode control Mode2:0 000 001 010 011 100 101 110 111 4:3 StopBits Number of stop bits selection StopBits1 ParityOdd Parity selection 0 Even parity (parity bit set on odd number of ‘1’s in data) 1 Odd parity (parity bit set on even number of ‘ ...
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... ST20-GP1 Read/Write 83/116 ...
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... ST20-GP1 ASCStatus register The ASCStatus register determines the cause of an interrupt. ASCStatus ASC base address + #14 Bit Bit field Function 0 RxBufFull Receiver buffer full flag 1 TxEmpty Transmitter empty flag 2 TxBufEmpty Transmitter buffer empty flag 3 ParityError Parity error flag 4 FrameError Framing error flag ...
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... Parallel input/output The ST20-GP1 device has 6 bits of Parallel Input/Output (PIO), each bit is programmable as an input or an output. The input bits can be compared against a register and an interrupt generated when the value is not equal. 14.1 PIO Port Each of the bits of the PIO port has a corresponding bit in the PIO registers associated with the port. These registers hold: output data for the port (POut) ...
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... ST20-GP1 PIn register The data read from this register will give the logic level present on an input pin at the start of the read cycle to this register. The read data will be the last value written to the register irrespective of the pin configuration selected. ...
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... When enabled, if input data bit 4 is different to PComp4 then an interrupt is generated. 5 PMask5 When set to 1, the compare function for the internal interrupt for the port is enabled. When enabled, if input data bit 5 is different to PComp5 then an interrupt is generated. Table 14.4 PComp register format Table 14.5 PMask register format ST20-GP1 Read/Write Read/Write 87/116 ...
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... The byte-wide parallel port defaults to input (to the ST20-GP1) when the ST20-GP1 is reset (with the notRST pin) to prevent contention, and can be used for DMA functions without interfering with memory bank 2 ...
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... Mode 0 DMA mode (reset state) 1 EMI mode Table 15.1 PlinkEmi register format PlinkIO Direction 0 inputs (reset state) 1 outputs Table 15.2 PlinkIO register format PlinkMode Protocol 00 Idle (reset state) 01 Dreq/Dack mode 10 Valid/Ack mode 11 Direct mode Table 15.3 PlinkMode register format ST20-GP1 Read/Write Read/Write Read/Write 89/116 ...
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... The sequence of events for a Dreq/Dack output is outlined below. 1 PlinknotReq (Dreq), input to ST20, is taken low by the external ASIC. 2 The ST20-GP1 asserts the PlinknotAck (Dack) output low. The ASIC can then take PlinknotReq (Dreq) high. 3 Following PlinknotAck (Dack) going low, the data in the DMA buffer is applied to the output pins ...
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... The external device can then drive PlinknotReq (Ivalid) low. 4 PlinknotAck (Iack) can be taken low. The external device can then initiate the next transac- tion. PlinknotAck (Qvalid) PlinknotReq (Qack) old data PlinkData0-7 PlinknotReq (Ivalid) PlinknotAck (Iack) PlinkData0-7 ST20 Output valid data ST20 Input Figure 15.2 Valid/Ack protocol ST20-GP1 91/116 ...
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... ST20-GP1 15.4.3 Direct DMA protocol In this mode the PLink becomes an unsynchronized (i.e. direct action) bus. The PlinknotAck output still behaves were acknowledging a real transfer. The PlinknotReq signal has no effect in this mode of operation. In this mode PlinknotAck is active high. The initial (inactive) state of the pin is low. ...
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... Configuration register addresses This chapter lists all the ST20-GP1 configuration registers and gives the addresses of the registers. The complete bit format of each of the registers and its functionality is given in the relevant chapter. The registers can be examined and set by the devlw (device load word) and devsw (device store word) instructions ...
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... ASC1BaudRate ASC1TxBuffer ASC1RxBuffer ASC1Control ASC1IntEnable ASC1Status POut Set_POut Clear_POut PIn PC1 Set_PC1 Clear_PC1 PComp Set_PComp Clear_PComp PMask Set_PMask Clear_PMask PlinkEmi PlinkIO PlinkMode Table 16.1 ST20-GP1 configuration register addresses 94/116 Address Size Set #20000514 1 #20002000 32 #20002004 32 #20002008 32 #2000200C 32 #20002010 32 #20002020 32 #20002030 32 #20004000 ...
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... PRNphase4 PRNphase4WrEn #2000C054 PRNphase5 PRNphase5WrEn #2000C058 PRNphase6 PRNphase6WrEn #2000C05C PRNphase7 PRNphase7WrEn #2000C060 PRNphase8 PRNphase8WrEn #2000C064 PRNphase9 PRNphase9WrEn #2000C068 PRNphase10 PRNphase10WrEn #2000C06C PRNphase11 PRNphase11WrEn Table 16.1 ST20-GP1 configuration register addresses Size Set Clear ...
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... NCOfrequency5 NCOfrequency6 NCOfrequency7 NCOfrequency8 NCOfrequency9 NCOfrequency10 NCOfrequency11 NCOphase0 NCO1phase NCOphase2 NCOphase3 NCOphase4 NCOphase5 NCOphase6 NCOphase7 NCOphase8 NCOphase9 NCOphase10 NCOphase11 PRNinitialVal0 PRNinitialVal1 DSPControl Table 16.1 ST20-GP1 configuration register addresses 96/116 Address Size Set #2000C080 18 #2000C084 18 #2000C088 18 #2000C08C 18 #2000C090 18 #2000C094 18 #2000C098 18 #2000C09C 18 #2000C0A0 ...
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... Load capacitance per pin l Notes 1 For a package junction to case thermal resistance of 14 C/W. 2 The nominal input clock frequency must be 16.368 MHz for the DSP module to function cor- rectly with the GPS satellites. Table 17.1 Absolute maximum ratings Table 17.2 Operating conditions ST20-GP1 Min Max Units Notes -0.5 4.5 V -0.5 4.5 V ...
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... ST20-GP1 DC specifications Symbol Parameter V Positive supply voltage during normal operation Positive supply voltage when device is off but real time DDoff clock is running. V Voltage at RTCVDD pin referred to GND. DDrtc during normal operation and notRST set to DDdiff DD DDrtc 1. V Input logic 1 for LPClockIn, notRST and test control pins. ...
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... The transition need not be monotonic, providing that the notRST pin is forced low during the whole period while the main VDD voltage is not within limits set in the DC operating conditions. Min Typical Table 17.4 AC Specification ST20-GP1 Max Units Notes 100 100 ...
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... The ST20-GP1 pays signal/noise ratio penalty by using 1-bit signal coding, there are then no further losses in the signal processing hardware. The fast sampling rate, with both in-phase and quadrature channels, results in the subsequent processing being 11 dB better signal to noise ratio, than earlier systems that sample at 2 MHz ...
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... Table 18.2 Time to first fix ST20-GP1 Time to first fix 90s 45s 1s ...
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... ST20-GP1 19 Timing specifications 19.1 EMI timings The timings are based load, and are taken at a threshold of 1.5 V. Symbol Parameter t Reference clock high to Address valid CHAV t Reference clock low to Strobe valid CLSV t Reference clock high to Strobe valid CHSV t Read Data valid to Reference clock high ...
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... Reference clock t CHAV MemAddr1-19 t CHSV notMemCE0-3 notMemOE0-3 notMemWB0-1 MemData0-15 (Read) t CHWDV MemData0-15 (Write) MemWait Figure 19.1 EMI timings t CLSV t CHRDX t RDVCH t WVCH t CHWX ST20-GP1 103/116 ...
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... ST20-GP1 19.2 Link timings Symbol Parameter t LinkOut rise time JQr t LinkOut fall time JQf t LinkIn rise time JDr t LinkIn fall time JDf t Buffered edge delay JQJD t Variation JQJD C LinkIn capacitance LIZ C LinkOut load capacitance LL Notes 1 This is the variation in the total delay through buffers, transmission lines, differential receiv- ers etc ...
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... CPUAnalyse setup before CPUReset AHRH t CPUAnalyse hold after CPUReset end RLAL notRST t CPUReset CPUAnalyse Figure 19.4 Reset and Analyse timings Min Table 19.3 Reset and Analyse timings RSTHRSTL t RHRL t AHRH ST20-GP1 Nom Max Units Notes ClockIn ClockIn ms ClockIn t RHRL t RLAL 105/116 ...
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... ST20-GP1 19.4 ClockIn timings Symbol Parameter t ClockIn pulse width low for PLL operation DCLDCH t ClockIn pulse width high for PLL operation DCHDCL t ClockIn rise time for PLL operation DCr t ClockIn fall time for PLL operation DCf t GPSIF valid before clock rising edge ...
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... PLink. PlinknotReq (Dreq) PlinknotAck (Dack) PlinkData0-7 (Output) PlinkData0-7 (Input) Figure 19.6 Byte-wide parallel port timings when using the Dreq/Dack protocol t PRLPAL t PALPAH t PALDOV t PALDIV ST20-GP1 Min Max Units 100 340 ...
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... ST20-GP1 19.5.2 Valid/Ack protocol In this mode the two control pins PlinknotReq (Qack/Ivalid) and PlinknotAck (Qvalid/Iack) are active high. The initial (inactive) state of the two control wires is low. Symbol Parameter PLink is output t PlinknotAck rising transition to PlinknotReq rising PAHPRH t PlinkData0-7 setup time before rising edge of PlinknotAck ...
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... PlinkData0-7 (Input) Figure 19.8 Byte-wide parallel port timings when using the Direct DMA protocol 16.4 Mhz Min 330 100 0 100 220 220 Table 19.7 Timings for Direct mode t PAHPAL t DOVPAL t DIVPAL ST20-GP1 32.7 Mhz Units Max Min Max 160 270 100 140 ns ...
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... Signals names are prefixed by not if they are active low, otherwise they are active high. Supplies Pin VDD GND Clocks Pin LowPowerClockIn LowPowerClockOsc LowPowerStatus notWdReset RTCVDD Table 20.2 ST20-GP1 low power controller and real time clock pins System services Pin ClockIn SpeedSpeed0-1 notRST CPUReset CPUAnalyse ErrorOut Table 20.3 ST20-GP1 system services pins Links Pin ...
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... TXD0-1 RXD0-1 Parallel IO Pin PIO0-5 Byte wide parallel port Pin PlinkData0-7 PlinknotReq PlinknotAck PlinkOut Table 20.9 ST20-GP1 byte wide parallel port pins Application specific Pin GPSIF Table 20.10 ST20-GP1 application specific pins Miscellaneous Pin ConnectToGND Table 20.11 ST20-GP1 miscellaneous pins In/Out Function ...
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... ST20-GP1 21 Package specifications The ST20-GP1 is available in a 100 pin plastic quad flat pack (PQFP) package. 21.1 ST20-GP1 package pinout Figure 21.1 ST20-GP1 100 pin PQFP package pinout 112/116 ...
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... ST20-GP1 NOTES MIN - 0.134 - - 0.110 0.120 - 0.015 - 0.009 - 0.951 0.787 0.791 0.742 - REF - 0.715 0.551 0.555 0.486 - REF 0.026 - BSC - 0.004 - 7 0.031 0.037 ...
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... ST20-GP1 Figure 21.2 100 pin PQFP package dimensions 114/116 ...
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... Device ID The identification code for the ST20-GP1 5191011, where manufacturing revision number reserved by SGS-THOMSON. See Table 22.1. bit 31 a Mask rev ST20 family reserved indicates SGS-THOMSON part, 1 indicates customer part. ...
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... ST20-GP1 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the conse- quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice ...