sc2608 Semtech Corporation, sc2608 Datasheet - Page 7

• Manufacturer Part Number: sc2608
• Description: Sc2608 Simple, Synchronous Voltage Mode Pwm Controller
• Manufacturer: Semtech Corporation

Compensation Network Design
Compensation Network Design
POWER MANAGEMENT
A note to the user is needed: The device cannot restart until
both COMP and SENSE are low, to prevent start up into a
charged output. In the event of an overcurrent condition,
the output is quickly discharged by the load, therefore bringing
SENSE below the 300mV threshold. If the COMP pin is pulled
low by an external device (such as an open-drain logic gate
used for system shutdown), and SENSE is high(above 300mV)
is high while COMP is low, then the SC2608 turns on the low
side FET to discharge the output before changing to shutdown
or soft-start mode. The low side FET turns off when SENSE
drops below 300mV and the converter remains in the tri-
state condition until COMP is released. Although this
shutdown technique can be used successfully on the SC2608,
the system designer using COMP for external shutdown will
need to consider the load on the low side FET when
discharging the output capacitor bank. For large capacitor
bank, this peak current can be quite large as it is limited only
by the R
this event is quite short, and has been shown in the lab to
have no detrimental effect on the performance of the external
FETs.
Disabling the output by pulling down COMP/SS pin is only
recommended when the output capacitor bank is not too
large.
Compensation Network Design
Compensation Network Design
Compensation Network Design
Fig. 4. SC2608 small signal model.
The control model of SC2608 is depicted in Fig. 4. This
model can also be used to generate loop gain Bode plots.
The bandgap reference is 0.8V and trimmed to +/-1%
accuracy. The desired output voltage can be achieved by
setting the resistive divider network, R1 and R2. The error
amplifier is transconductance type with fixed gain of:
The compensation network includes a resistor and a ca-
pacitor in series, which terminates the output of the error
amplifier to the ground.
The PWM gain is inversion of the ramp amplitude, and
Applications Information (Cont.)
©
this gain is given by:
2005 Semtech Corp.
VBG
0.8V
DS(ON)
of the low side FET. Fortunately the duration of
E/A
R
C
G
m
=
Ci
G_PWM
. 0
007
V
VIN
A
L
Rc
Co
Ro
R1
R2
7
where the ramp amplitude is fixed at 1 volts.
The total control loop-gain can then be derived as
follows:
The task here is to properly choose the compensation net-
work for a nicely shaped loop-gain Bode plot. The follow-
ing design procedures are recommended to accomplish
the goal:
(1) Calculate the corner frequency of the output filter:
(2) Calculate the ESR zero frequency of the output filter
capacitor:
(3) Check that the ESR zero frequency is not too high.
If this condition is not met, the compensation structure
may not provide loop stability. The solution is to add some
electrolytic capacitors to the output capacitor bank to cor-
rect the output filter corner frequency and the ESR zero
frequency. In some cases, the filter inductance may also
need to be adjusted to shift the filter corner frequency. It
is not recommended to use only high frequency multi-layer
ceramic capacitors for output filter.
(4) Choose the loop gain cross over frequency (0 dB fre-
quency). It is recommended that the crossover frequency
is always less than one fifth of the switching frequency :
If the transient specification is not stringent, it is better to
choose a crossover frequency that is less than one tenth of
the switching frequency for good noise immunity.
resistor in the compensation network can then be calcu-
lated as:
when
T
( )
s
=
G
m
•
F
R
G
o
=
pwm
<
G
pwm
F
•
V
esr
in
•
1
V
•
<

 

in
V
V
•
F
G
bg
H
F
F
F
F
o
G
o
X
5
esr
sw
pwm

•  

c
esr
m
_
( )
=
OVER
s
•
=
H

 

2
=
<
=
c
π
2
F
F
( )
V
esr
s
π
=
o
R
F
ramp
R
1
1
•
1
1
5

 

LC
5
+
SW
c
2
1
1
C
•
•
+
sC
F
1
o
o

 

s
1
SW

 

F
R
+
X
F
c
_
C
esr
sC
OVER
o
+
i
1

•  

R
L
+
o
www.semtech.com




sR
SC2608

 

V
V
+
c
bg
o
C
s
o
2




LC
o

 

1
+
The
R
R
c
o

 
