sc2449iswtrt Semtech Corporation, sc2449iswtrt Datasheet - Page 18

• Manufacturer Part Number: sc2449iswtrt
• Description: Sc2449 Bi-phase/dual Controller
• Manufacturer: Semtech Corporation

Good layout is necessary for successful implementa-
tion of the SC2449 bi-phase/dual controller. Important
layout guidelines are listed below.
1). The high power parts should be laid out first. The para-
sitic inductance of the pulsating power current loop (start
from positive end of the input capacitor, to top MOSFET,
then to bottom MOSFET back to power ground) must be
minimized. The high frequency input capacitors and top
MOSFETs should be close to each other. The freewheel-
ing Schottky diode, the bottom MOSFET snubber, and
the bottom MOSFET should be placed close to each other.
The MOSFET gate drive and current sense loop areas
should be minimized. The gate drive trace should be
short and wide.
2). The layout of the two phases should be made as sym-
metrical as possible. The SC2449 controller should be
placed in the center of the two phases. Please see evalu-
ation board layout as an example.
POWER MANAGEMENT
Control Loop Design (Cont.)
Layout Guidelines
2007 Semtech Corp.
p h ase i ( )
m ag i ( )
1 3 5
1 8 0
1 0 0
4 5
9 0
5 0
5 0
0
0
1 0
1 0
Fig. 2. Bode plot of the loop
1 0 0
1 0 0
L o o p G ain P h ase (D egree)
L o o p G ain M ag (dB )
1 1 0
1 1 0
18
3
3
3). Separate ground planes for analog and power should
be provided. Power current should avoid running over
the analog ground plane. The AGND is star connected to
the PGND at the converter output to provide best pos-
sible ground sense. Refer to the application schematics,
certain components should be connected directly to the
AGND.
4). If a multi-layer PCB is used, power layer and ground
layer are recommended to be adjacent to each other.
Typically the power layer is on the top, followed by the
ground layer. This results in the least parasitic inductance
in the MOSFET-capacitor power loop, and reduces the
ringing on the phase node. The rest of the layers could
be used to run DC supply traces and signal traces.
An example of a two-layer PCB layout is given below to
illustrate these layout principles.
F
F
i
i
1 1 0
1 1 0
4
4
1 1 0
1 1 0
5
5
1 1 0
1 1 0
6
6
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SC2449