74LVC74ABQ,115 NXP Semiconductors, 74LVC74ABQ,115 Datasheet - Page 3
![IC DUAL D FF POS-EDGE 14DHVQFN](/photos/6/94/69489/568-14dhvqfn_sot762_sml.jpg)
74LVC74ABQ,115
Manufacturer Part Number
74LVC74ABQ,115
Description
IC DUAL D FF POS-EDGE 14DHVQFN
Manufacturer
NXP Semiconductors
Series
74LVCr
Type
D-Typer
Datasheet
1.74LVC74AD118.pdf
(16 pages)
Specifications of 74LVC74ABQ,115
Package / Case
14-VQFN Exposed Pad, 14-HVQFN, 14-SQFN, 14-DHVQFN
Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
250MHz
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
2
Logic Family
LVC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
2.5 ns at 3.3 V
High Level Output Current
- 24 mA
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
1.2 V
Delay Time - Propagation
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Delay Time - Propagation
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
74LVC74ABQ-G
74LVC74ABQ-G
935273502115
74LVC74ABQ-G
935273502115
NXP Semiconductors
5. Pinning information
Table 2.
74LVC74A_6
Product data sheet
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
Fig 5. Pin configuration for SO14 and (T)SSOP14
CC
Pin description
GND
1RD
1CP
1SD
1Q
1Q
1D
5.1 Pinning
5.2 Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
74
001aad106
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true output
complement output
ground (0 V)
complement output
true output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
supply voltage
14
13
12
11
10
9
8
V
2RD
2D
2CP
2SD
2Q
2Q
CC
Rev. 06 — 4 June 2007
Dual D-type flip-flop with set and reset; positive-edge trigger
Fig 6. Pin configuration for DHVQFN14
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
index area
terminal 1
1CP
1SD
1D
1Q
1Q
Transparent top view
2
3
4
5
6
GND
74
(1)
74LVC74A
13
12
11
10
9
001aad107
© NXP B.V. 2007. All rights reserved.
2RD
2D
2CP
2SD
2Q
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