ds2155gt-r Maxim Integrated Products, Inc., ds2155gt-r Datasheet - Page 192

• Manufacturer Part Number: ds2155gt-r
• Description: Ds2155 T1/e1/j1 Single-chip Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Gapped-Clock Enable (RGPCKEN)
Bit 1/Receive Channel-Data Format (RDATFMT)
Bit 2/Transmit Gapped-Clock Enable (TGPCKEN)
Bit 3/Transmit Channel-Data Format (TDATFMT)
Bit 4/ Unused, must be set to 0 for proper operation
Bit 5/ Unused, must be set to 0 for proper operation
Bit 6/Interrupt Disable (INTDIS). This bit is convenient for disabling interrupts without altering the various
interrupt mask register settings.
Bit 7/Transmit Multiframe Sync Source (TMSS). Should be set = 0 only when transmit hardware signaling is
enabled.
0 = RCHCLK functions normally
1 = enable gapped bit-clock output on RCHCLK
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in seven out of the 8 bits)
0 = TCHCLK functions normally
1 = enable gapped bit-clock output on TCHCLK
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in seven out of the 8 bits)
0 = interrupts are enabled according to the various mask register settings
1 = interrupts are disabled regardless of the mask register settings
0 = elastic store is source of multiframe sync
1 = framer or TSYNC pin is source of multiframe sync
TMSS
7
0
INTDIS
6
0
CCR3
Common Control Register 3
72h
5
0
-
4
0
-
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TDATFMT
3
0
TGPCKEN
2
0
RDATFMT
1
0
RGPCKEN
0
0