MX29LV040 Macronix, MX29LV040 Datasheet
MX29LV040
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MX29LV040 Summary of contents
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... Automatically program and verify data at specified address • Erase suspend/Erase Resume GENERAL DESCRIPTION The MX29LV040 is a 4-mega bit Flash memory orga- nized as 512K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. The MX29LV040 is packaged in 32-pin PLCC and TSOP ...
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... A13 4 A14 5 A17 6 WE# 7 VCC 8 MX29LV040 A18 9 A16 10 A15 11 A12 SECTOR STRUCTURE Table 1. MX29LV040 SECTOR ADDRESS TABLE Sector A18 A17 A16 SA0 SA1 SA2 SA3 SA4 SA5 SA6 ...
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... BLOCK DIAGRAM CONTROL CE# INPUT OE# WE# LOGIC ADDRESS LATCH A0-A18 AND BUFFER Q0-Q7 P/N:PM0722 MX29LV040 PROGRAM/ERASE HIGH VOLTAGE MACHINE STATE REGISTER MX29LV040 FLASH ARRAY ARRAY SOURCE COMMAND HV DATA Y-PASS GATE DECODER PGM SENSE DATA COMMAND AMPLIFIER HV DATA LATCH PROGRAM DATA LATCH I/O BUFFER 3 WRITE ...
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... The typical chip programming time at room temperature of the MX29LV040 is less than 10 seconds. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm ...
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... Table 1 and Table 2). The rest of address bits, as shown in table 3, are don't care. Once all neces- sary bits have been set as required, the programming equipment may read the corresponding identifier code on Q7~Q0. TABLE 2. MX29LV040 AUTOMATIC SELECT MODE OPERATION Description CE# OE# WE# Read Manufacture Code ...
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... TABLE 3. MX29LV040 COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Manufacture ID 4 555H AAH 2AAH Read Silicon ID 4 555H AAH 2AAH Sector Protect 4 555H AAH 2AAH Verify Program 4 555H AAH 2AAH Chip Erase 6 555H AAH 2AAH ...
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... Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 3 defines the valid register command TABLE 4. MX29LV040 BUS OPERATION DESCRIPTION Read Write Reset ...
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... The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. P/N:PM0722 MX29LV040 STANDBY MODE When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, ...
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... However, multiplexing high volt- age onto address lines is not generally desired system design practice. The MX29LV040 contains a Silicon-ID-Read operation to supple traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Fol- lowing the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H ...
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... If Q5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during Erase Suspend). P/N:PM0722 MX29LV040 SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the de- vice to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Au- tomatic Sector Erase command ...
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... Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information. P/N:PM0722 Q7 (Note1) Q7# Erase Suspend Read (Erase Suspended Sector) Data (Non-Erase Suspended Sector) Erase Suspend Program Q7# Q7# Q7# 11 MX29LV040 (Note2) Toggle 0 N/A No Toggle 0 Toggle 0 1 ...
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... Once the Automatic Program command is initiated, the next WE# pulse causes a transition to an active pro- gramming operation. Addresses are latched on the fall- P/N:PM0722 MX29LV040 ing edge, and data are internally latched on the rising edge of the WE# or CE#, whichever happens first. The rising edge of WE# or CE#, whichever happens first, also begins the programming operation ...
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... Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. P/N:PM0722 MX29LV040 When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output En- able (OE#) is asserted low ...
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... The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. Alterna- tively, it may choose to perform other system tasks. In P/N:PM0722 MX29LV040 this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Q5 ...
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... VCC and GND. P/N:PM0722 MX29LV040 POWER-UP SEQUENCE The MX29LV040 powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command se- quences. SECTOR PROTECTION The MX29LV040 features hardware sector protection. ...
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... CHIP UNPROTECT The MX29LV040 also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code recommended to protect all sectors before activating chip unprotect mode. To activate this mode, the programming equipment must force VID on control pin OE# and address pin A9 ...
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... C to +125 C V Supply Voltages CC V for regulated voltage range . . . . . +3 3 for full voltage range +2 3 Operating ranges define those limits between which the functionality of the device is guaranteed. 17 MX29LV040 ). . . . . . . . . . . . + - + REV. 1.3, DEC. 20, 2004 ...
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... V 0.7xVCC VCC+ 0.3 V 11.5 12.5 V 0.45 V 0.85xVCC VCC-0.4 18 MX29LV040 CONDITIONS VIN = 0V VIN = 0V VOUT = 0V CONDITIONS VIN = VSS to VCC VCC=VCC max; A9=12.5V VOUT = VSS to VCC, VCC=VCC max CE#=VIL, OE#=VIH @5MHz @1MHz CE#=VIL, OE#=VIH CE#;VCC 0.3V CE#; VCC 0.3V VIH=VCC 0.3V;VIL=VSS 0.3V VCC=3.3V IOL = 4.0mA, VCC= VCC min IOH = -2mA, VCC=VCC min IOH = -100uA, VCC min REV ...
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... TTL gate + 30pF (Including scope and jig) for 29LV040-70 & 29LV040- 55R. • Reference levels for measuring timing: 1.5V. P/N:PM0722 VCC = 2.7V~3. VCC = 3.3V 5% for MX29LV040-55R) 29LV040-55R 29LV040-70 29LV040-90 MIN. MAX. MIN. MAX. MIN ...
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... Figure 2. SWITCHING TEST WAVEFORMS 3.0V 1. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM0722 CL 6.2K ohm CL=100pF Including jig capacitance CL=30pF for MX29LV040-70 & MX29LV040-55R TEST POINTS INPUT 20 MX29LV040 2.7K ohm +3.3V DIODES=IN3064 OR EQUIVALENT 1.5V OUTPUT REV ...
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... Figure 3. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL P/N:PM0722 MX29LV040 tRC ADD Valid tACC tCE tOE tOEH tACC DATA Valid 21 tDF tOH HIGH Z REV. 1.3, DEC. 20, 2004 ...
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... Sector Address Load Time NOTES: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM0722 VCC = 2.7V~3. VCC = 3.3V 5% for MX29LV040-55R) 29LV040-55R 29LV040-70 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit ...
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... C, VCC = 3.3V 5% for MX29LV004T/B-55R) 29LV040-55R 29LV040-70 MIN. MAX. MIN. MAX 9(Typ.) 9(Typ.) 0.7(Typ.) 0.7(Typ.) 23 MX29LV040 29LV040-90 29LV040-12 MIN. MAX. MIN. MAX.UNIT 90 120 ...
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... Figure 4. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE# VIL tOES CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM0722 ADD Valid tAH tWPH tWP tCWC tCH tDS tDH DIN 24 MX29LV040 REV. 1.3, DEC. 20, 2004 ...
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... DATA# during programming and DATA# after programming on Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling, timing waveform) Read Status Data (last two cycle) tAS PA tAH tCH tWHWH1 tWP tWPH tDS tDH A0h PD 25 MX29LV040 PA PA Status DOUT REV. 1.3, DEC. 20, 2004 ...
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... Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM0722 MX29LV040 START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES No Last Address ? YES Auto Program Completed 26 REV ...
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... P/N:PM0722 PA for program SA for sector erase 555 for chip erase Data# Polling tAS tAH tWHWH1 or 2 tCPH tBUSY tDH A0 for program PD for program 55 for erase 30 for sector erase 10 for chip erase 27 MX29LV040 PA DOUT Q7 REV. 1.3, DEC. 20, 2004 ...
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... Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling, timing waveform) Read Status Data tAS 555h tAH tCH tWHWH2 tWP tWPH tDS tDH 55h 10h 28 MX29LV040 Progress Complete REV. 1.3, DEC. 20, 2004 ...
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... Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data Pall from System NO Data=FFh ? YES Auto Chip Erase Completed 29 MX29LV040 REV. 1.3, DEC. 20, 2004 ...
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... Device outputs 0 dur- ing erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling, timing waveform) tAS Sector Sector Sector Address 0 Address 1 Address n tAH tBAL tWPH 30h 30h 30h 30 MX29LV040 Read Status Data VA VA tWHWH2 In Progress Complete REV. 1.3, DEC. 20, 2004 ...
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... Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address NO Last Sector to Erase YES Data Poll from System NO Data=FFh YES Auto Sector Erase Completed 31 MX29LV040 REV. 1.3, DEC. 20, 2004 ...
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... P/N:PM0722 START Write Data B0H ERASE SUSPEND NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H Delay 10ms (note) ERASE RESUME Continue Erase Another NO Erase Suspend ? YES 32 MX29LV040 REV. 1.3, DEC. 20, 2004 ...
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... Figure 13. TIMING WAVEFORM FOR SECTOR PROTECT A1 A6 12V 3V A9 tVLHT 12V 3V OE# tVLHT WE# CE# Data A18-A12 P/N:PM0722 tWPP 1 tOESP Sector Address 33 MX29LV040 Verify tVLHT 01H F0H tOE REV. 1.3, DEC. 20, 2004 ...
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... Figure 14. SECTOR PROTECTION ALGORITHM No PLSCNT=32? Yes Device Failed P/N:PM0722 MX29LV040 START Set Up Sector Addr PLSCNT=1 OE#=VID, A9=VID, CE#=VIL A6=VIL Activate WE# Pulse Time Out 150us Set WE#=VIH, CE#=OE#=VIL A9 should remain VID Read from Sector Addr=SA, A1=1 No Data=01H? Yes Protect Another Sector? Remove VID from A9 ...
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... A9 tVLHT A6 12V 3V OE# tVLHT WE# CE# Data A17-A12 Notes: tWPP1 (Write pulse width for sector protect)=100ns min. tWPP2 (Write pulse width for sector unprotect)=100ns min. P/N:PM0722 tWPP 2 tOESP 35 MX29LV040 Verify tVLHT 00H F0H tOE Sector Address REV. 1.3, DEC. 20, 2004 ...
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... Figure 16. CHIP UNPROTECTED ALGORITHM Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM0722 MX29LV040 START Protect All Sectors PLSCNT=1 Set OE#=A9=VID CE#=VIL, A6=1 Activate WE# Pulse Time Out 50ms Set OE#=CE#=VIL A9=VID,A1=1 Set Up First Sector Addr Read Data from Device ...
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... WRITE OPERATION STATUS Figure 17. DATA# POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM0722 Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? Yes Read Q7~Q0 Add.=VA Yes Q7 = Data ? (2) No FAIL 37 MX29LV040 Pass REV. 1.3, DEC. 20, 2004 ...
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... Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM0722 Start Read Q7-Q0 Read Q7-Q0 (Note oggle Bit oggle ? YES Q5= 1? YES (Note 1, oggle bit Q6= T oggle? YES Program/Erase operation Complete Reset Command 38 MX29LV040 REV. 1.3, DEC. 20, 2004 ...
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... VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle. 2. CE# must be toggled when DATA# polling. P/N:PM0722 VA tDF tOH Complement Complement True Status Data Status Data True 39 MX29LV040 VA High Z Valid Data High Z Valid Data REV. 1.3, DEC. 20, 2004 ...
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... VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 2. CE# must be toggled when toggle bit toggling. P/N:PM0722 tRC VA VA tOE tDF tOH Valid Status Valid Status (second read) (first raed) 40 MX29LV040 VA VA Valid Data Valid Data (stops toggling) REV. 1.3, DEC. 20, 2004 ...
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... Figure 21 for Erase and Erase Suspend Operations Enter Embedded Erase Erasing Suspend Erase WE NOTES: The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended P/N:PM0722 MX29LV040 Enter Erase Erase Suspend Program Resume Erase Erase Suspend Suspend Read Program 41 Erase ...
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... VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A17 VIL CE# VIH VIL VIH WE# VIL VIH OE# VIL VIH DATA VIL Q0-Q15 P/N:PM0722 tACC tCE tOE tOH DATA OUT C2H/00C2H 42 MX29LV040 tDF tOH DATA OUT B9H/BAH (Byte) 22B9H/22BAH (Word) REV. 1.3, DEC. 20, 2004 ...
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... Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. Table 14. DATA RETENTION Parameter Description Data Retention Time P/N:PM0722 MX29LV040 LIMITS MIN. TYP.(2) MAX.(3) 0 ...
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... MX29LV040QC-55R 55 MX29LV040QC-70 70 MX29LV040QC-90 90 MX29LV040QC-12 120 MX29LV040TI-70 70 MX29LV040TI-90 90 MX29LV040TI-12 120 MX29LV040QI-70 70 MX29LV040QI-90 90 MX29LV040QI-12 120 MX29LV040TC-70G 70 MX29LV040TC-90G 90 MX29LV040TC-12G 120 MX29LV040QC-70G 70 MX29LV040QC-90G 90 MX29LV040QC-12G 120 MX29LV040TI-70G 70 MX29LV040TI-90G 90 MX29LV040TI-12G 120 MX29LV040QI-70G 70 MX29LV040QI-90G 90 MX29LV040QI-12G 120 P/N:PM0722 OPERATING STANDBY CURRENT MAX.(mA) CURRENT MAX.(uA ...
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... PACKAGE INFORMATION P/N:PM0722 MX29LV040 45 REV. 1.3, DEC. 20, 2004 ...
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... P/N:PM0722 MX29LV040 46 REV. 1.3, DEC. 20, 2004 ...
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... To modify sector erase operation timing waveform and add tBAL timing in the Erase/Program AC table 1 modify 32-PLCC package information 2. To added PB-free part no. in ordering information 1 modified 55ns EPN from MX29LV040TC/QC-55 to MX29LV040TC/QC-55R 1 corrected tRC definition from MAX. to MIN. P/N:PM0722 MX29LV040 ...
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... MX29LV040 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...