MBM29LV004TC Fujitsu Media Devices, MBM29LV004TC Datasheet - Page 23

• Manufacturer Part Number: MBM29LV004TC
• Description: 4M (512K X 8) BIT
• Manufacturer: Fujitsu Media Devices

Notes: 1. Performing successive read operations from any address will cause DQ
RY/BY
Ready/Busy
RESET
Hardware Reset
Program
Erase
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
Erase-Suspend Program
The MBM29LV004TC/BC provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands with the exception of the Erase Suspend command. If the MBM29LV004TC/BC are placed in an
Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resister to V
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
The MBM29LV004TC/BC devices may be reset by driving the RESET pin to V
requirement and has to be kept low (V
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional t
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ
toggle.
Mode
MBM29LV004TC
2
bit. However, successive reads from the erase-suspended sector will cause DQ
RH
before it will allow read access. When the RESET pin is low, the devices will
IL
) for at least 500 ns in order to properly reset the internal state machine.
DQ
DQ
DQ
0
1
7
7
7
-70/-90/-12
/MBM29LV004BC
Toggle (Note 1)
Toggle
Toggle
DQ
1
6
IL
. The RESET pin has a pulse
6
to toggle.
1 (Note 2)
Toggle
Toggle
DQ
1
-70/-90/-12
2
CC
CC
.
.
2
to
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