MBM29DL400BC Fujitsu Media Devices, MBM29DL400BC Datasheet
MBM29DL400BC
Related parts for MBM29DL400BC
MBM29DL400BC Summary of contents
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... When addresses remain stable, automatically switch themselves to low power mode. • Low V write inhibit 2 • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device Embedded Erase TM and Embedded Program 8/256K /MBM29DL400BC -55/-70/-90/-12 2 PROMs TM are trademarks of Advanced Micro Devices, Inc. DS05-20866-2E 16) BIT -55/-70/-90/-12 (Continued) ...
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... Hardware method disables any combination of sectors from program or erase operations • Sector Protection Set function by Extended sector protection command • Fast Programming Function by Extended Command • Temporary sector unprotection Temporary sector unprotection via the RESET pin. PACKAGE 48-pin plastic TSOP (I) Marking Side (FPT-48P-M19) 2 /MBM29DL400BC -55/-70/-90/-12 48-pin plastic TSOP (I) Marking Side (FPT-48P-M20) -55/-70/-90/-12 ...
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... Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29DL400TC/BC memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. /MBM29DL400BC -55/-70/-90/-12 -55/-70/-90/-12 supply. 12 and 5 ...
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... MBM29DL400BC Sector Architecture -55/-70/-90/-12 (X8) (X16) 7FFFFH 3FFFFH 64K byte/32K word 70000H 38000H 64K byte/32K word 60000H 30000H 64K byte/32K word 50000H 28000H 64K byte/32K word 40000H ...
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... BLOCK DIAGRAM Bank 2 Address RESET State WE Control CE Command OE Register BYTE Bank 1 Address /MBM29DL400BC -55/-70/-90/-12 MBM29DL400TC/MBM29DL400BC +0.3 V -55 -70 –0.3 V +0.6 V — — –0 Cell Matrix (Bank 2) X-Decoder RY/BY Status X-Decoder Cell Matrix (Bank 1) -55/-70/-90/-12 — — -90 -12 90 ...
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... MBM29DL400TC/MBM29DL400BC 12 Standard Pinout FPT-48P-M19 24 (Marking Side MBM29DL400TC/MBM29DL400BC 12 Reverse Pinout FPT-48P-M20 -55/-70/-90/- BYTE ...
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... MBM29DL400TC -55/-70/-90/-12 LOGIC SYMBOL RY/BY RESET BYTE /MBM29DL400BC Table 1 MBM29DL400TC/BC Pin Configuration Pin Function Address Inputs - Data Inputs/Outputs Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output Hardware Reset Pin/Temporary Sector ...
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... Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See Table 8. 2. Refer to the section on Sector Protection can 3.3 V ± 10 also used for the extended sector protection. 8 /MBM29DL400BC -55/-70/-90/- ...
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... Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29DL400 T C -55 DEVICE NUMBER/DESCRIPTION MBM29DL400 4Mega-bit (512K 3.0 V-only Read, Program, and Erase /MBM29DL400BC -55/-70/-90/-12 PFTN PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout SPEED OPTION ...
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... Under this condition the current is consumed is less than 5 A max. Once the RESET pin is taken high, the device requires t of wake up time before outputs are valid for read access the standby mode the outputs are in the high impedance state, independent of the OE input. 10 /MBM29DL400BC -55/-70/-90/- with zero latency ...
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... IL identifier code (MBM29DL400TC = 0CH and MBM29DL400BC = 0FH for 8 mode; MBM29DL400TC = 220CH and MBM29DL400BC = 220FH for 16 mode). These two bytes/words are given in the tables 5.1 and 5.2. All identifiers for manufactures and device will exhibit odd parity with DQ the proper device codes when executing the autoselect, A ...
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... Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses. Table 5 .2 Expanded Autoselect Code Table Type Code Manufacturer’s Code 04H (B) 0CH A MBM29DL400TC (W) 220CH Device Code (B) 0FH A MBM29DL400BC (W) 220FH Sector Protection 01H (B): Byte mode (W): Word mode 12 /MBM29DL400BC -55/-70/-90/- Byte ...
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... The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the taken away from the RESET pin, all the previously protected sectors will be protected again. See Figures 17 and 26. /MBM29DL400BC -55/-70/-90/-12 , while and ...
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... Please note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality. 14 /MBM29DL400BC -55/-70/-90/-12 ) for at least 500 ns in order to properly reset the internal state machine. IL before it will allow read access ...
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... SA11 SA12 SA13 Note: The address range (BYTE = /MBM29DL400BC -55/-70/-90/-12 Sector Address Tables (MBM29DL400TC) Sector Size ( bytes/ Address Range K words 64/32 00000H to 0FFFFH X X 64/32 10000H to 1FFFFH X X 64/32 20000H to 2FFFFH X ...
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... Bank 1 SA3 SA2 SA1 SA0 Note: The address range (BYTE = /MBM29DL400BC -55/-70/-90/-12 Sector Address Tables (MBM29DL400BC) Sector Size (Kbytes/ Address Range Kwords 64/32 70000H to 7FFFFH 64/32 60000H to 6FFFFH 64/32 50000H to 5FFFFH ...
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... This command is valid while Fast Mode. 6. The system should generate the following address patterns: Word Mode: 555H or 2AAH to addresses A Byte Mode: AAAH or 555H to addresses A 7. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. /MBM29DL400BC -55/-70/-90/-12 MBM29DL400TC/BC Command Definitions Fourth Bus Second Bus ...
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... Following the command write, a read cycle from address (BA)00H retrieves the manufacture code of 04H. A read cycle from address (BA)01H for 16((BA)02H for 8) returns the device code (MBM29DL400TC = 0CH and MBM29DL400BC = 0FH for 8 mode; MBM29DL400TC = 220CH and MBM29DL400BC = 220FH for 16 mode). (See Tables 5.1 and 5.2.) All manufacturer and device codes will exhibit odd parity with DQ or unprotection) will be informed by address (BA)02H for 16 ((BA)04H for 8) ...
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... DQ device returns to read the mode. Chip Erase Time; Sector Erase Time Figure 22 illustrates the Embedded Erase /MBM29DL400BC -55/-70/-90/-12 TM Algorithm using typical command strings and bus operations. is “1” (See Write Operation Status section.) at which time the ...
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... Writing the Erase Resume command (30H) resumes the erase operation. The bank addresses of sector being erasing or suspending should be set when writting the Erase Suspend or Erase Resume command. 20 /MBM29DL400BC -55/-70/-90/-12 to determine if the sector erase timer window is still open, see section 3 TM Algorithm using typical command strings and bus operations ...
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... If the output data is logical “0”, please repeat to 0 write extended sector protect command (60H) again. To terminate the operation necessary to set RESET pin /MBM29DL400BC -55/-70/-90/-12 bit will be at logic “1”, and and DQ ...
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... DQ is Fujitsu internal use only /MBM29DL400BC -55/-70/-90/-12 will not toggle if an address from a non-erasing sector is consectively read toggling in the case of [1] and [3]. In case of [2], the data toggled in the [1] and [3]. In case of [2], the data of memory cell is ...
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... If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs and then drop back into read mode, having changed none of the data. Either toggling will cause the DQ cause the DQ to toggle. 6 /MBM29DL400BC -55/-70/-90/-12 . Upon completion of the Embedded Program 7 is active for approximately 100 s, then the bank returns to read mode one instant of time and then that byte’ ...
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... Program operation is in progress. The behavior of these two status bits, along with that follows: 24 /MBM29DL400BC -55/-70/-90/-12 never stops toggling. Once the devices have exceeded timing limits, the 6 , can be used to determine whether the devices are in the Embedded Erase 6 to toggle during the Embedded Erase Algorithm. If the ...
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... Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form V and power-down transitions or system noise. /MBM29DL400BC -55/-70/-90/- ...
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... logical one. Power-Up Write Inhibit Power-up of the devices with The internal state machine is automatically reset to the read mode on power-up. 26 /MBM29DL400BC -55/-70/-90/-12 power-up and power-down, a write cycle is locked out for V CC < the command register is disabled and all internal program/erase circuits ...
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... No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. /MBM29DL400BC -55/-70/-90/-12 , OE, RESET (Note 1) ................... –0 and RESET pins are – ...
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... V Figure +2.0 V Figure 2 +14.0 V +13 +0 This waveform is applied for A Figure 3 28 /MBM29DL400BC -55/-70/-90/- Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform OE, and RESET. 9 Maximum Positive Overshoot Waveform 2 -55/-70/-90/- ...
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... Embedded Algorithm (program or erase progress Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. Applicable for only V applying Embedded Algorithm (program or erase progress. (@5 MHz) /MBM29DL400BC -55/-70/-90/-12 Test Conditions Max ...
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... Input rise and fall times Input pulse levels: 0 3.0 V Timing measurement reference level Input: 1.5 V Output:1.5 V Device Under Test Note including jig capacitance (MBM29DL400TC/BC-55/-70 100 pF including jig capacitance (MBM29DL400TC/BC-90/-12 /MBM29DL400BC -55/-70/-90/-12 Test Setup — Min Max Max. IL — Max. ...
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... Rise Time to V VIDR — t Voltage Transition Time (Note 2) VLHT — t Write Pulse Width (Note 2) WPP — Setup Time to WE Active (Note 2) OESP /MBM29DL400BC -55/-70/-90/-12 Description Min. Min. Min. Min. Min. Min. Min. Read Min. Toggle and Data Polling Min. Min. ...
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... BYTE Switching High to Output Active FHQV — t Program/Erase Valid to RY/BY Delay BUSY — t Delay Time from Embedded Output Enable EOE Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Protection operation. 32 /MBM29DL400BC -55/-70/-90/-12 Description Max. Max. Max. -55/-70/-90/-12 MBM29DL400TC/BC Unit -55 -70 -90 -12 Min ...
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... MBM29DL400TC SWITCHING WAVEFORMS • Key to Switching Waveforms WAVEFORM Addresses OEH WE High-Z Outputs Figure 5.1 /MBM29DL400BC -55/-70/-90/-12 INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from from May Will Be Change Changing from from “H” or “L” ...
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... MBM29DL400TC Addresses RESET Outputs Figure 5.2 34 /MBM29DL400BC -55/-70/-90/- Addresses Stable t ACC High-Z AC Waveforms for Hardware Reset/Read Operations -55/-70/-90/- Output Valid ...
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... D is the output of the data written to the device. OUT 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the 16 mode. (The addresses differ from 8 mode.) Figure 6 Alternate WE Controlled Program Operations /MBM29DL400BC Data Polling ...
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... D is the output of the data written to the device. OUT 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the 16 mode. (The addresses differ from 8 mode.) Figure 7 36 /MBM29DL400BC -55/-70/-90/-12 3rd Bus Cycle Data Polling 555H ...
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... VCS V CC Notes the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte) for Chip Erase. 2. These waveforms are for the 16 mode. (The addresses differ from 8 mode.) Figure 8 AC Waveforms Chip/Sector Erase Operations /MBM29DL400BC 2AAH 555H 555H ...
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... MBM29DL400TC Data Data RY/ Valid Data (The device has completed the Embedded operation). 7 Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations 38 /MBM29DL400BC -55/-70/-90/- OEH WHWH1 Output Flag 0 6 BUSY -55/-70/-90/-12 t ...
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... Toggle DQ /DQ Data 6 2 Data t BUSY RY/ stops toggling (The device has completed the Embedded operation). 6 Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations /MBM29DL400BC AHT ASO AHT AS t CEPH t OEPH t OEH Toggle Toggle Data ...
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... MBM29DL400TC CE WE RY/BY Figure 11 RY/BY Timing Diagram during Program/Erase Operations WE RESET RY/BY 40 /MBM29DL400BC -55/-70/-90/-12 The rising edge of the last write pulse READY Figure 12 RESET/RY/BY Timing Diagram -55/-70/-90/-12 Entire programming or erase operations t BUSY t RB ...
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... Figure 13 Timing Diagram for Word Mode Configuration CE BYTE t ELFL Figure 14 Timing Diagram for Byte Mode Configuration BYTE Figure 15 /MBM29DL400BC -55/-70/-90/-12 Data Output Data Output ( ( FHQV Data Output Data Output (DQ ...
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... VLHT WE CE Data t VCS V CC SAX : Sector Address for initial sector SAY : Sector Address for next sector Note byte mode Figure 16 42 /MBM29DL400BC -55/-70/-90/-12 t VLHT t WPP t OESP t CSP AC Waveforms for Sector Protection -55/-70/-90/-12 SAY t VLHT 01H t OE ...
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... WE Note read from the erase-suspended sector. 2 Valid DQ Output Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1. BA2: Address of Bank 2. Figure 18 /MBM29DL400BC Program or Erase Command Sequence Unprotection period Read Command BA2 ...
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... Erase Embedded Suspend Erasing WE Erase Toggle DQ and with Note read from the erase-suspended sector /MBM29DL400BC -55/-70/-90/-12 Enter Erase Suspend Program Erase Suspend Erase Erase Suspend Read Suspend Program Figure -55/-70/-90/-12 Erase Resume Erase Erase ...
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... Add Data 60H SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 s (min) Figure 20 Extended Sector Protection Timing Diagram /MBM29DL400BC -55/-70/-90/- SPAX TIME-OUT 40H 60H -55/-70/-90/-12 SPAX SPAY 60H 01H ...
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... MBM29DL400TC EMBEDDED ALGORITHMS Increment Address * : The sequence is applied for The addresses differ from Figure 21 46 /MBM29DL400BC -55/-70/-90/-12 Start Write Program Command Sequence (See below) Data Polling Device No Last Address ? Yes Programming Completed Program Command Sequence* (Address/Command): 555H/AAH 2AAH/55H 555H/A0H Program Address/Program Data 16 mode ...
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... Chip Erase Command Sequence* (Address/Command): 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H * : The sequence is applied for The addresses differ from 8 mode. Figure 22 /MBM29DL400BC -55/-70/-90/-12 Start Write Erase Command Sequence (See below) Data Polling or Toggle Bit Successfully Completed Erasure Completed Individual Sector/Multiple Sector* Erase Command Sequence (Address/Command): ...
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... MBM29DL400TC Note rechecked even /MBM29DL400BC -55/-70/-90/-12 Start Read ( Byte address for programming 0 7 Addr Any of the sector addresses within Yes DQ = Data Any of the sector addresses within Yes Read ( Addr Yes DQ = Data Fail Pass = “ ...
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... MBM29DL400TC -55/-70/-90/-12 Note rechecked even changing to “1” Figure 24 /MBM29DL400BC Start Read ( Bank address being executed 0 7 Addr Toggle 6 ? Yes Yes Read ( Addr Toggle 6 ? Yes Fail Pass = “1” because DQ may stop toggling at the same time as ...
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... MBM29DL400TC Increment PLSCNT PLSCNT = 25? Remove V Write Reset Command Device Failed * : byte mode /MBM29DL400BC -55/-70/-90/-12 Start Setup Sector Addr PLSCNT = RESET = = Activate WE Pulse Time out 100 should remain V ...
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... MBM29DL400TC -55/-70/-90/-12 Notes: 1. All protected sectors are unprotected. 2. All previously protected sectors are protected once again. Figure 26 Temporary Sector Unprotection Algorithm /MBM29DL400BC Start RESET = V ID (Note 1) Perform Erase or Program Operations RESET = V IH Temporary Sector Unprotection Completed (Note 2) -55/-70/-90/-12 51 ...
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... Device is Operating in Temporary Sector Unprotection Mode Increment PLSCNT No PLSCNT = 25? Yes Remove V from RESET ID Write Reset Command Device Failed Figure 27 52 /MBM29DL400BC -55/-70/-90/-12 Start RESET = V ID Wait Extended Sector Protection Entry? Yes To Setup Sector Protection Write XXXH/60H PLSCNT = 1 To Sector Protection ...
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... MBM29DL400TC FAST MODE ALGORITHM Increment Address * : The sequence is applied for The addresses differ from 8 mode. Figure 28 Embedded Program /MBM29DL400BC -55/-70/-90/-12 Start 555H/AAH 2AAH/55H 555H/20H XXXH/A0H Program Address/Program Data Data Polling Device No Verify Byte? Yes No Last Address ? Yes Programming Completed (BA) XXXH/90H XXXH/F0H 16 mode. ...
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... Chip Programming Time Program/Erase Cycle TSOP(I) PIN CAPACITANCE Parameter Parameter Description Symbol C Input Capacitance IN C Output Capacitance OUT C Control Pin Capacitance IN2 Note: Test conditions T = 25° 1.0 MHz A 54 /MBM29DL400BC -55/-70/-90/-12 Limits Min. Typ. Max. — — 16 360 — 8 300 — 4.2 12.5 100,000 — ...
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... LEAD No. 1 INDEX 24 19.00±0.20 (.748±.008) 0.10(.004) * 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) 1996 FUJITSU LIMITED F48030S-2C-2 C /MBM29DL400BC -55/-70/-90/- Resin protrusion. (Each Side: 0.15 (.006)max) 48 Details of "A" part "A" 0.15(.006 12.00±0.20 (.472±.008) 11.50REF (.460) 0.50(.0197) TYP 0.15± ...
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... Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9811 FUJITSU LIMITED Printed in Japan 56 /MBM29DL400BC -55/-70/-90/-12 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use ...