LTC4224-2 Linear Technology, LTC4224-2 Datasheet - Page 7

• Manufacturer Part Number: LTC4224-2
• Description: Compact Dual Low Voltage Hot Swap Controller
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
V
The LTC4224 is powered from the higher of its two supply
pins, V
ply voltage as low as 1V, while the other supply is 2.7V or
greater. If both supplies are tied together, the part derives
its power from both equally. The Functional Diagram shows
the V
ment. It is designed to ensure swift and smooth internal
power switchover from one supply to the other.
Turn-On Sequence
Separate ON1 and ON2 pins allow the V
supplies to be turned on in any order. The power supplies
delivered to a plug-in card are controlled by external N-
channel MOSFETs, Q1 and Q2. For X2/XENPAK defi ned
optical transceiver modules, it has been specifi ed that the
MOD DETECT pin pulls low inside the module through a
1k resistor (R
conditions must be satisfi ed to turn on the MOSFETs.
First, V
lockout level for longer than an internal UV turn-on delay
of 160ms. Next, if V
low (<0.8V), a debounce delay of 10ms is started. If V
drops below 0.8V or ONn goes high before the end of the
10ms debounce delay, the debounce delay is restarted the
next time these pins are properly conditioned.
When the 10ms debounce delay expires, the external
MOSFET is turned on by charging up the GATE with a
CC
Selection
CC
5V/DIV
5V/DIV
2V/DIV
5V/DIV
5V/DIV
GATE1
GATE2
ON1/2
V
V
CC1
CC1
OUT1
OUT2
selection circuit in an ideal diode OR-ing arrange-
or V
and V
Figure 2. Normal Power-Up Sequence
MOD_DET
CC2
CC2
must exceed the 2.4V V
.This allows the part to control a sup-
CCn
), as shown in Figure 1. Several
is greater than 0.8V and ONn is
5ms/DIV
CC
422412 F02
CC1
undervoltage
and V
CC2
CCn
10μA charge pump generated current source. When the
GATE voltage reaches the MOSFET threshold voltage, the
inrush current can build up quickly as the GATE continues
to rise. The ACL amplifi er actively controls the gate volt-
age to maintain 25mV across the sense resistor. In this
condition, the inrush current is given by:
As the inrush current charges up the load capacitor, the
output rises with a corresponding increase in gate voltage.
When the supply is no longer in current limit, an internal
charge pump pulls the gate to 5.5V above the higher of V
or V
shows a typical start-up sequence with C
= 150μF , R
The inrush current can be reduced to below the current
limit level by adding an external gate capacitor as shown
in Figure 3.
GATE capacitor C
the inrush current. However, C
high frequency self oscillation in Q1. A 10Ω resistor, R
shown in Figure 3 can be used to prevent the oscillation.
To be effective, R
The voltage at the GATE pin rises with a slope equal to I
C
capacitor C
GATE
I
C
INRUSH
CC2
GATE
. For a given supply inrush current I
Figure 3. Inrush Current Control by Gate Capacitor
to achieve a low resistance power path. Figure 2
=
LOAD1
=
LOAD
I
INRUSH
5V
LTC4224-1/LTC4224-2
I
R
GATE
25mV
SENSE
, C
GATE
= 4.7Ω and R
G
V
CC1
GATE
0.015Ω
needs to be laid out close to Q1.
LTC4224
• C
R1
provides gate slew rate control to limit
I
GATE
SENSE1
LOAD
can be calculated according to:
GATE1
Q1
LOAD2
GATE
R
10Ω
G
could cause parasitic
C
= 2Ω.
GATE
422412 F03
C
LOAD
INRUSH
LOAD1
= C
and load
LOAD2
422412fa
GATE
G
7
CC1
, as
/