LTC3736-2 Linear Technology, LTC3736-2 Datasheet - Page 23

• Manufacturer Part Number: LTC3736-2
• Description: Synchronous Controller
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
increased by decreasing C
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736-2. These items are illustrated in the layout dia-
gram of Figure 13. Figure 14 depicts the current wave-
forms present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
2) The signal and power grounds should be kept separate.
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the
power loop of the other channel. Ideally, the drains of
the P- and N-channel FETs should be connected close
to one another with an input capacitor placed across
the FET sources (from the P-channel source to the N-
channel source) right at the FETs. It is better to have
two separate, smaller valued input capacitors (e.g.,
two 10µF—one for each channel) than it is to have a
single larger valued capacitor (e.g., 22µF) that the
channels share with a common connection.
The signal ground consists of the feedback resistor
dividers, I
The power grounds consist of the (–) terminal of the
input and output capacitors and the source of the N-
channel MOSFET. Each channel should have its own
OUT
, causing a rapid drop in V
TH
compensation networks and the SGND pin.
U
U
C
. The output voltage settling
W
OUT
. No regulator can
U
LOAD
).
3) Put the feedback resistors close to the V
4) The current sense traces (SENSE
5) Keep the switch nodes (SW1, SW2) and the gate driver
power ground for its power loop (as described above
in item 1). The power grounds for the two channels
should connect together at a common point. It is most
important to keep the ground paths with high switch-
ing currents away from each other.
The PGND pins on the LTC3736-2 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
trace connecting the top feedback resistor (R
output capacitor should be a Kelvin trace. The I
compensation components should also be very close
to the LTC3736-2.
Kelvin connections right at the P-channel MOSFET
source and drain.
nodes (TG1, TG2, BG1, BG2) away from the small-
signal components, especially the opposite channel’s
feedback resistors, I
and the current sense pins (SENSE
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 13. LTC3736-2 Layout Diagram
10
11
12
1
2
3
4
5
6
7
8
9
SW1
IPRG1
V
I
IPRG2
PLLLPF
SGND
V
TRACK
V
I
PGOOD
TH1
TH2
FB1
IN
FB2
LTC3736EGN-2
SYNC/FCB
SENSE1
SENSE2
RUN/SS
PGND
PGND
PGND
SW2
BG1
BG2
TG1
TG2
TH
+
+
24
23
22
21
20
19
18
17
16
15
14
13
compensation components,
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+
C
C
OUT1
OUT2
LTC3736-2
and SW) should be
+
and SW).
C
C
C
VIN1
VIN2
MN1
MN2
VIN
+
+
FB
37362 F13
L1
L2
pins. The
B
V
V
MP1
MP2
23
) to the
OUT1
OUT2
37362fa
TH
V
IN