AD9522-3 Analog Devices, Inc., AD9522-3 Datasheet
AD9522-3
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AD9522-3 Summary of contents
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... GHz. An external 3.3 V/5 V VCO/VCXO 2.4 GHz can also be used. 1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-3 is used referring to that specific member of the AD9522 family. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...
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... AD9522-3 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics ................................................................ 8 Timing Diagrams ..................................................................... 8 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................................................................ 9 Clock Output Absolute Phase Noise (Internal VCO Used Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ...
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... Frequency Planning Using the AD9522 .................................. 80 Using the AD9522 Outputs for ADC Clock Applications .... 80 LVDS Clock Distribution ........................................................... 80 CMOS Clock Distribution ......................................................... 81 Outline Dimensions ........................................................................ 82 Ordering Guide ........................................................................... 82 Rev Page AD9522-3 ...
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... AD9522-3 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5. (min) and maximum (max) values are given over full VS and T POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ VS 3.135 3.3 VCP VS RSET Pin Resistor 4.12 CPRSET Pin Resistor 5.1 BYPASS Pin Capacitor ...
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... Register 0x019[5:3]; see Table 52 Off 365 ps 486 ps 608 ps 730 ps 852 ps 976 ps 1101 ps Rev Page AD9522-3 is possible by changing CP is possible by changing < VCP − 0 the voltage on the CP (charge CP CP < VCP − 0 ...
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... AD9522-3 Parameter PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVDS Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVDS Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in ...
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... VS − 0.1 V 0.1 V 2.7 V 0.5 V Rev Page AD9522-3 Test Conditions/Comments Termination = 100 Ω across differential pair Differential (OUT, OUT) The AD9522 outputs toggle at higher frequencies, but the output amplitude may not meet the V specification See Figure 21 Output shorted to GND Single-ended; termination = 10 pF ...
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... AD9522-3 TIMING CHARACTERISTICS Table 5. Parameter LVDS OUTPUT RISE/FALL TIMES Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVDS OUTPUT LVDS For All Divide Values Variation with Temperature 1 OUTPUT SKEW, LVDS OUTPUTS LVDS Outputs That Share the Same Divider ...
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... Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns −102 dBc/Hz −114 dBc/Hz −122 dBc/Hz −129 dBc/Hz −135 dBc/Hz −140 dBc/Hz −150 dBc/Hz Input slew rate > 1 V/ns −125 dBc/Hz −136 dBc/Hz −144 dBc/Hz −152 dBc/Hz −157 dBc/Hz −160 dBc/Hz −164 dBc/Hz Rev Page AD9522-3 ...
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... AD9522-3 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVDS ABSOLUTE PHASE NOISE VCO = 2250 MHz; Output = 750 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 1985 MHz; Output = 662 MHz @ 1 kHz Offset ...
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... Integration bandwidth = 12 kHz to 20 MHz 263 fs rms Calculated from SNR of ADC method Broadband jitter 242 fs rms Calculated from SNR of ADC method Broadband jitter Distribution section only; does not include PLL and VCO 289 fs rms Calculated from SNR of ADC method Broadband jitter Rev Page AD9522-3 ...
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... AD9522-3 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12. Parameter LVDS OUTPUT ADDITIVE TIME JITTER CLK = 500 MHz; VCO DIV = 5; LVDS = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = On CMOS OUTPUT ADDITIVE TIME JITTER CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz; ...
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... MIN (0.7 × VS) 400 kHz μs μs μs μs μs μs 300 ns 300 ns ns This is a minor deviation from the original I²C specification of 100 ns minimum 880 ns This is a minor deviation from the original I²C specification minimum 400 pF AD9522-3 levels MAX ...
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... AD9522-3 PD, SYNC, AND RESET PINS Table 15. Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming SYNC TIMING Pulse Width Low SERIAL PORT SETUP PINS: SP1, SP0 Table 16. ...
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... Delta between divider bypassed (divide-by-1) and divide-by-2 to divide-by- Rev Page AD9522-3 = 250 MHz; VCO = 2000 MHz; VCO divider = 2; OUT = 62.5 MHz; VCO = 2000 MHz; VCO divider = 2; OUT = 200 MHz; VCO divider = 2; one LVDS output OUT = 200 MHz; VCO divider bypassed; one LVDS OUT = 62 ...
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... AD9522-3 ABSOLUTE MAXIMUM RATINGS Table 19. With Parameter or Pin Respect to VS GND VCP, CP GND REFIN, REFIN GND RSET, LF, BYPASS GND CPRSET GND CLK, CLK GND CLK CLK SCLK/SCL, SDIO/SDA, SDO, CS GND OUT0, OUT0, OUT1, OUT1, GND OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, ...
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... Along with CLK, this pin is the differential input for the clock distribution section. Along with CLK, this pin is the differential input for the clock distribution section single-ended input is connected to the CLK pin, connect a 0.1 μF bypass capacitor from this pin to ground. Rev Page AD9522-3 48 OUT3 (OUT3A) 47 OUT3 (OUT3B) ...
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... AD9522-3 Input/ Pin Pin No. Output Type Mnemonic 15 I 3.3 V CMOS 3.3 V CMOS SCLK/SCL 17 I/O 3.3 V CMOS SDIO/SDA 18 O 3.3 V CMOS SDO 19 GND GND 20 I Three-level SP1 logic 21 I SP0 Three-level logic 22 I 3.3 V CMOS EEPROM 23 I 3.3 V CMOS RESET 24 I 3.3 V CMOS LVDS or OUT9 (OUT9A) ...
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... Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. The exposed die pad must be connected to GND. Rev Page AD9522-3 ...
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... AD9522-3 TYPICAL PERFORMANCE CHARACTERISTICS 275 3 CHANNELS—6 LVDS 250 225 3 CHANNELS—3 LVDS 200 175 2 CHANNELS—2 LVDS 150 125 1 CHANNEL—1 LVDS 100 75 0 200 400 600 FREQUENCY (MHz) Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), Channel and VCO Divider Bypassed, LVDS Outputs Terminated 100 Ω Across Differential Pair 240 2 CHANNELS— ...
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... Figure 16. CMOS Output V 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 135 140 145 0 Rev Page AD9522-3 122.58 122.78 122.98 123.18 FREQUENCY (MHz) LBW = 127 kHz 3.0 mA 1720 MHz CP VCO VS_DRV = 3.3V VS_DRV = 3.135V VS_DRV = 2.5V VS_DRV = 2.35V 1k RESISTIVE LOAD (Ω) (Static) vs. R (to Ground) ...
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... AD9522-3 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 0.5 1.0 1.5 TIME (ns) Figure 18. LVDS Differential Voltage Swing @ 800 MHz Output Terminated 100 Ω Across Differential Pair 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0 TIME (ns) Figure 19. CMOS Output with 10 pF Load @ 25 MHz 2pF LOAD 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0 TIME (ns) Figure 20. CMOS Output with 2 pF and 10 pF Load @ 250 MHz ...
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... Figure 27. Additive (Residual) Phase Noise, CLK-to-LVDS @ 200 MHz, Divide-by-5 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 28. Additive (Residual) Phase Noise, CLK-to-LVDS @ 800 MHz, Divide-by-1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 29. Additive (Residual) Phase Noise, CLK-to-CMOS @ 50 MHz, Divide-by-20 AD9522-3 10M 100M 10M 100M 10M 100M ...
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... AD9522-3 –100 –110 –120 –130 –140 –150 –160 10 100 1k 10k 100k FREQUENCY (Hz) Figure 30. Additive (Residual) Phase Noise, CLK-to-CMOS @ 250 MHz, Divide-by-4 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @ 1720 MHz; PFD = 15.36 MHz; LBW = 40 kHz; LVDS Output = 122.88 MHz – ...
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... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9522-3 ...
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... AD9522-3 DETAILED BLOCK DIAGRAM REF_SEL REFERENCE SWITCHOVER REF1 STATUS REF2 OPTIONAL REFIN STATUS BUF REFIN AMP LOW DROPOUT BYPASS REGULATOR (LDO) LF CLK CLK PD DIGITAL EEPROM SYNC LOGIC RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO ...
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... Use the VCO divider as the source for the distribution section 0x018[ Reset VCO calibration and issue IO_UPDATE 0x232[ (not necessary for the first time after power-up but must be done subsequently) 0x018[ Initiate VCO calibration, issue IO_UPDATE 0x232[ Rev Page AD9522-3 CP ...
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... AD9522-3 REF_SEL REFERENCE SWITCHOVER REF1 STATUS REF2 OPTIONAL REFIN STATUS BUF REFIN AMP LOW DROPOUT BYPASS REGULATOR (LDO) LF CLK CLK PD DIGITAL EEPROM SYNC LOGIC RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522 VS GND RSET ...
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... PLL. Make sure to select the proper PFD polarity for the VCO/VCXO being used. Table 25. Setting the PFD Polarity Register Description 0x010[ PFD polarity positive (higher control voltage produces higher frequency) 0x010[ PFD polarity negative (higher control voltage produces lower frequency) Rev Page AD9522-3 ...
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... AD9522-3 REF_SEL REFERENCE SWITCHOVER REF1 STATUS REF2 OPTIONAL REFIN STATUS BUF REFIN AMP LOW DROPOUT BYPASS REGULATOR (LDO) LF CLK CLK PD DIGITAL EEPROM SYNC LOGIC RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522 VS GND RSET ...
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... PLL. Make sure to select the proper PFD polarity for the VCO being used. Table 28. Setting the PFD Polarity Register 0x010[ 0x010[ Rev Page AD9522-3 Description PLL asynchronous power-down (PLL off ) Set VCO divider = 2 Use the VCO divider CLK selected as the source Description PLL normal operation (PLL on) PLL settings ...
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... AD9522-3 REF_SEL REFERENCE SWITCHOVER REF1 STATUS REF2 OPTIONAL REFIN STATUS BUF REFIN AMP LOW DROPOUT BYPASS REGULATOR (LDO) LF CLK CLK PD DIGITAL EEPROM SYNC LOGIC RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522 Figure 39. High Frequency Clock Distribution or External VCO > 1600 MHz (Mode 2) ...
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... The antibacklash pulse width is set by 0x017[1:0]. An important limit to keep in mind is the maximum frequency allowed into the PFD. The maximum input frequency into the PFD is a function of the antibacklash pulse setting, as specified in the phase/frequency detector (PFD) parameter in Table 2. Rev Page AD9522-3 CPRSET VCP LD LOCK DETECT HOLD ...
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... AD9522-3 Charge Pump (CP) The charge pump is controlled by the PFD. The PFD monitors the phase and frequency relationship between its two inputs and tells the CP to pump up or pump down to charge or discharge the integrating node (part of the loop filter). The integrated and ...
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... R, A, and B counters. It can also be reset by a SYNC operation. VCO/VCXO Feedback Divider The N divider is a combination of a prescaler (P) and two counters, A and B. The total divider value × where P can 16, or 32. Rev Page AD9522-3 ...
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... AD9522-3 Prescaler The prescaler of the AD9522 allows for two modes of operation: a fixed divide (FD) mode and a dual modulus (DM) mode where the prescaler divides by P and ( and 3, 4 and 5, 8 and 9, 16 and 17 and 33}. The prescaler modes of operation are given in Table 52, 0x016[2:0]. Not all modes are available at all frequencies (see Table 2) ...
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... The user can asynchronously enable individual clock outputs only when CSDLD is high. To enable this feature, set the appropriate bits in the enable output on the CSDLD registers (0x0FC and 0x0FD). AD9522 110µA DLD LD PIN COMPARATOR Figure 45. Current Source Digital Lock Detect Rev Page AD9522 3. OUT ...
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... AD9522-3 External VCXO/VCO Clock Input (CLK/ CLK ) This differential input is used to drive the AD9522 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors. CLOCK INPUT STAGE VS CLK CLK 2.5kΩ ...
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... R and N dividers for faster settling of the PLL and reduces frequency errors during settling. Because the prescaler is not reset, this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out. Rev Page AD9522-3 ...
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... AD9522-3 After leaving holdover, the loop then reacquires lock and the LD pin must go high (if 0x01D[ before it can reenter holdover. The holdover function always responds to the state of the currently selected reference (0x01C). If the loop loses lock during a reference switchover (see the Reference Switchover section), holdover is triggered briefly until the next reference clock edge at the PFD ...
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... VCO frequency results. • Whenever system calibration is desired. The VCO is designed to operate properly over extremes of temperature even when it is first calibrated at the opposite extreme. However, a VCO calibration can be initiated at any time, if desired. Rev Page AD9522-3 ...
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... AD9522-3 REFIN/ REFIN MUX1 LF DIVIDE CLK/CLK 1 ZERO DELAY OPERATION Zero delay operation aligns the phase of the output clocks with the phase of the external PLL reference input. There are two zero delay modes on the AD9522: internal and external. ...
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... VCO divider is used not possible to select the VCO without using the VCO divider. Table 31. Operation Modes 0x1E1 Mode [ Rev Page AD9522-3 PLL LF DIVIDE CLK CLK 1 0 CLOCK DISTRI- BUTION DISTRIBUTION CLOCK ...
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... AD9522-3 Clock Frequency Division The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the VCO or CLK to the output is the product of the VCO divider ( and 6) and the division of the channel divider ...
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... Synchronizing the Outputs— Function section). Table 38. Setting Phase Offset and Division Start Divider High (SH) 0 0x191[4] 1 0x194[4] 2 0x197[4] 3 0x19A[4] Rev Page AD9522-3 D Output Duty Cycle X Disable Div DCC = 1 Disable Div DCC = 1)/ 50%, requires 1)/ 50%, requires 1 X%)/(2 × ...
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... AD9522-3 Let Δ = delay (in seconds). t Δ = delay (in cycles of clock signal at input period of the clock signal at the input of the divider seconds). Φ × SH[ × PO[ × PO[ × PO[ × PO[0] The channel divide by is set high cycles and M = low cycles. Case 1 For Φ ...
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... TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT CHANNEL DIVIDER OUTPUT STATIC CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT Figure 54. LVDS Output Simplified Equivalent Circuit with Rev Page AD9522-3 CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT CLOCKING 1 11 ...
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... AD9522-3 CMOS Output Drivers The user can also individually configure each LVDS output as a pair of CMOS outputs, which provides CMOS outputs. When an output is configured as CMOS, CMOS Output A and CMOS Output B are automatically turned on. For a given differential pair, either CMOS Output A or Output B can be turned on or off independently ...
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... Powering down a clock channel also automatically powers down the drivers connected to it. The register map details the individual power-down settings for each output channel. These settings are found in 0x192[2], 0x195[2], 0x198[2], and 0x19B[2]. Rev Page AD9522-3 ...
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... AD9522-3 SERIAL CONTROL PORT The AD9522 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9522 serial control port is compatible with most synchronous transfer formats, including Philips I2C, Motorola® SPI®, and Intel® ...
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... A repeated start (Sr) condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. Rev Page AD9522-3 ACKNOWLEDGE FROM SLAVE-RECEIVER ...
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... AD9522-3 Data Transfer Format Send byte format—the send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. ...
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... determined by W1:W0 the read operation is in streaming mode, continuing until CS is raised. Streaming mode does not skip over reserved or blank registers. The readback data is valid on the falling edge of SCLK. Rev Page AD9522-3 ...
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... AD9522-3 The default mode of the AD9522 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin also possible to set the AD9522 to unidirectional mode (0x000[ and 0x000[0] = 1). In unidirectional mode, the readback data appears on the SDO pin ...
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... D1 D0 REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA t C DON'T CARE DON'T CARE REGISTER ( DATA AD9522-3 LSB I0 A0 DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE ...
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... AD9522 SCLK SDIO Table 45. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between the CS falling edge and SCLK rising edge (start of communication cycle) ...
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... EEPROM. This allows VCO calibration to start automatically after register loading. A valid input reference signal must be present during VCO calibration. To verify that the data transfer has completed correctly, the user can verify that 0xB01[ value this register indicates a data transfer error. Rev Page AD9522-3 ...
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... AD9522-3 PROGRAMMING THE EEPROM BUFFER SEGMENT The EEPROM buffer segment is a register space on the AD9522 that allows the user to specify which groups of registers are stored to the EEPROM during EEPROM programming. Normally, this segment does not need to be programmed by the user. Instead, ...
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... Address [15:8] of the second group of registers Address [7:0] of the second group of registers Number of bytes [6:0] of the third group of registers Address [15:8] of the third group of registers Address [7:0] of the third group of registers IO_UPDATE operational code (0x80) End-of-data operational code (0xFF) Rev Page AD9522-3 Bit 2 Bit 1 Bit 0 (LSB) ...
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... AD9522-3 THERMAL PERFORMANCE Table 47. Thermal Parameters for the 64-Lead LFCSP Symbol Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board θ Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) JA θ Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) JMA θ ...
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... Prescaler P Antibacklash pulse width VCO calibration divider VCO calibration now N path delay LD pin control REFMON pin control Enable Enable Enable REF2 REF1 differential reference Unused Enable Enable external holdover holdover AD9522-3 Default Value (Hex N/A N/A N ...
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... AD9522-3 Addr (Hex) Parameter Bit 7 (MSB) 01E PLL_CTRL_9 01F PLL_Readback Unused (read-only) Output Driver Control 0F0 OUT0 control OUT0 format 0F1 OUT1 control OUT1 format 0F2 OUT2 control OUT2 format 0F3 OUT3 control OUT3 format 0F4 OUT4 control OUT4 format 0F5 ...
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... Disable power-on SYNC Unused Unused Unused EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1) EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2) Rev Page AD9522-3 Bit 2 Bit 1 Bit 0 (LSB) Divider 1 high cycles Divider 1 phase offset Channel 1 Reserved Disable ...
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... AD9522-3 Addr (Hex) Parameter Bit 7 (MSB) A05 EEPROM EEPROM Buffer Segment Register 6 (default: Bits[7:0] of starting register address for Group 2) Buffer Segment Register 6 A06 EEPROM 0 Buffer Segment Register 7 A07 EEPROM EEPROM Buffer Segment Register 8 (default: Bits[15:8] of starting register address for Group 3) Buffer Segment ...
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... EEPROM error checking (read-only) B02 EEPROM Control 1 B03 EEPROM Control 2 Bit 6 Bit 5 Bit 4 Bit 3 Unused Unused Unused Unused Rev Page AD9522-3 Bit 2 Bit 1 Bit 0 (LSB) Unused STATUS_ EEPROM Unused EEPROM data error Soft_EEPROM Enable (self-clearing) EEPROM write Unused REG2EEPROM (self-clearing) ...
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... AD9522-3 REGISTER MAP DESCRIPTIONS Table 49 through Table 59 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is indicated by squared brackets. For example, [3] refers to Bit 3 and [5:2] refers to the range of bits from Bit 5 through Bit 2. ...
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... Charge Pump Mode High impedance state. Force source current (pump up). Force sink current (pump down). Normal operation (default). Mode Normal operation; this mode must be selected to use the PLL. Asynchronous power-down (default). Unused. Synchronous power-down. Rev Page AD9522-3 ...
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... AD9522-3 Reg. Addr (Hex) Bit(s) Name Description 016 [3] B counter B counter bypass. This is only valid when operating the prescaler in FD mode. bypass [ normal (default). [ counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. 016 [2:0] Prescaler P Prescaler dual modulus and FD = fixed divide ...
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... LVL DLD (active low LVL Holdover active (active low LVL LD pin comparator output (active low). Antibacklash Pulse Width (ns) 2.9 (default) 1.3 6.0 2.9 PFD Cycles to Determine Lock 5 (default 255 VCO Calibration Clock Divider (default) Rev Page AD9522-3 ...
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... AD9522-3 Reg. Addr (Hex) Bit(s) Name Description 018 [0] VCO calibration Bit used to initiate the VCO calibration. This bit must be toggled from the active registers. The now sequence to initiate a calibration follows: program to 0, followed by an IO_UPDATE bit (Register 0x232[0]); then program to 1, followed by another IO_UPDATE bit (Register 0x232[0]). This sequence gives complete control over when the VCO calibration occurs relative to the programming of other registers that can impact the calibration (default = 0) ...
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... REF1 frequency) AND (status REF2 frequency LVL (DLD) AND (status of selected reference) AND (status of VCO LVL Status of VCO frequency (active high LVL Selected reference (low = REF1, high = REF2 LVL DLD; active low. Rev Page AD9522-3 ...
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... AD9522-3 Reg. Addr (Hex) Bit(s) Name Description [4] [ 01C [7] Disable Disables or enables the switchover deglitch circuit. switchover [ enable the switchover deglitch circuit (default). ...
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... VCO frequency is less than the threshold. [ VCO frequency is greater than the threshold. [3] Selects Which Channel Divider to Use in the External Zero-Delay Path 0 Select Channel Divider 0 (default). 1 Select Channel Divider 1. 0 Select Channel Divider 2. 1 Select Channel Divider 3 Rev Page AD9522-3 ...
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... AD9522-3 Reg. Addr (Hex) Bit(s) Name Description 01F [2] REF2 frequency Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency > threshold set by Register 0x01A[6]. (read-only) [ REF2 frequency is less than the threshold frequency. [ REF2 frequency is greater than the threshold frequency. ...
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... Forces divider output to high. This requires that ignore SYNC also be set. [ divider output forced to low (default). [ divider output forced to high. Selects clock output to start high or start low. [ start low (default). [ start high. Phase offset (default: 0x0). Rev Page AD9522-3 ...
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... AD9522-3 Reg. Addr (Hex) Bit(s) Name 192 [2] Channel 0 power-down 192 [0] Disable Divider 0 DCC 193 [7:4] Divider 1 low cycles 193 [3:0] Divider 1 high cycles 194 [7] Divider 1 bypass 194 [6] Divider 1 ignore SYNC 194 [5] Divider 1 force high 194 [4] Divider 1 start high 194 [3:0] Divider 1 phase offset 195 ...
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... Description [2] [ normal operation (default). [ power down. Rev Page AD9522-3 Divide 2 (default Output static 1 (bypass) Output static ...
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... AD9522-3 Reg. Addr (Hex) Bit(s) Name 1E1 [3] Power-down VCO clock interface Powers down the interface block between VCO and clock distribution. 1E1 [2] Power-down VCO and CLK 1E1 [1] Select VCO or CLK 1E1 [0] Bypass VCO divider Table 56. System Reg. Addr (Hex) Bit(s) Name ...
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... B03 [0] REG2EEPROM Transfers data from the buffer register to the EEPROM (self-clearing). [ setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process reset by the I²C master after the data transfer is done. Rev Page AD9522-3 ...
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... AD9522-3 APPLICATIONS INFORMATION FREQUENCY PLANNING USING THE AD9522 The AD9522 is a highly flexible PLL. When choosing the PLL settings and version of the AD9522, the following guidelines should be kept in mind. The AD9522 has four frequency dividers: the reference (or R) divider, the feedback (or N) divider, the VCO divider, and the channel divider ...
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... The AD9522 offers LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters. Rev Page AD9522-3 60.4Ω (1.0 INCH) 10Ω CMOS CMOS MICROSTRIP Figure 72 ...
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... AD9522-3 OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range AD9522-3BCPZ 1 −40°C to +85°C 1 AD9522-3BCPZ-REEL7 −40°C to +85°C 1 AD9522-3/PCBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 TOP VIEW BSC BSC SQ 0.50 0. 0.30 0.80 MAX 0.65 TYP 0.05 MAX ...
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... NOTES Rev Page AD9522-3 ...
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... AD9522-3 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07224-0-10/08(0) Rev Page ...