CA3306C Intersil Corporation, CA3306C Datasheet
CA3306C
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CA3306C Summary of contents
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... CLK PHASE REF REF © Intersil Corporation 1999 4-8 CA3306C 6-Bit, 15 MSPS, Flash A/D Converters o C) PACKAGE PKG. NO PDIP E18 PDIP E18 SOIC M20 SOIC M20 SBDIP D18 SBDIP D18 CLCC J20 ...
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... REF CENTER REF R/2 50k CLOCK PHASE ZENER 6.2V NOMINAL DIODE V SS Typical Application Circuit 560 +12V CLOCK +12V CA741CE CA3306, CA3306A, CA3306C 1 1 COMP 64 COMP 63 COMPARATOR COMP LATCHES 32 AND ENCODER LOGIC COMP 2 COMP 1 2 (SAMPLE UNKNOWN) 1 (AUTO BALANCE CA3306 ...
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... Gain Error (Unadjusted) CA3306, CA3306C (Note 2) CA3306A Gain Temperature Coefficient Offset Temperature Coefficient DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale) Maximum Conversion Speed CA3306C CA3306, CA3306A Maximum Conversion Speed CA3306C CA3306, CA3306A Allowable Input Bandwidth -3dB Input Bandwidth Signal to Noise Ratio, SNR ...
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... Output Data Hold Time Output Enable Time Output Disable Time, t DIS POWER SUPPLY CHARACTERISTICS I Current, Refer to Figure 4 CA3306C DD CA3306, CA3306A I Current DD NOTES: 1. OFFSET ERROR is the difference between the input voltage that causes the output code transition and (V 2. GAIN ERROR is the difference the input voltage that causes the 3F 3 ...
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... CLOCK IF PHASE IS LOW DATA CE1 CE2 t DIS DATA BITS 1-6 OF SAMPLE ENDS 1 CLOCK 2 OLD DATA OUTPUT FIGURE 3A. CLOCK OUTPUT CA3306, CA3306A, CA3306C DECODED DATA IS SHIFTED TO OUTPUT REGISTERS AUTO SAMPLE BALANCE DATA FIGURE 1. INPUT-TO-OUTPUT DIS ...
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... -10 - INPUT VOLTAGE (V) FIGURE 8. TYPICAL PEAK INPUT CURRENT AS A FUNCTION OF INPUT VOLTAGE CA3306, CA3306A, CA3306C 125 100 TEMPERATURE - PLASTIC REF ZENER NOT CONNECTED FIGURE 5. TYPICAL MAXIMUM AMBIENT TEMPERATURE FUNCTION OF SUPPLY VOLTAGE ...
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... FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 -50 - TEMPERATURE ( FIGURE 12. DATA DELAY vs TEMPERATURE 14.0 12.6 11.2 9.8 8.4 7.0 5.6 4.2 2.8 1.4 0.0 -40 -30 -20 - TEMPERATURE ( FIGURE 14 TEMPERATURE DD CA3306, CA3306A, CA3306C (Continued DISSIPATION LIMITED FIGURE 11. DEVICE CURRENT vs SAMPLE FREQUENCY 6 5.7 5.4 5.1 4.8 4.5 4.2 3.9 3.6 3.3 3 100 - ...
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... REF(CTR CA3306, CA3306A, CA3306C (Continued 15MHz S 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 f (MHz) I FIGURE 16. ENOB vs INPUT FREQUENCY Bit 6, Output (MSB). Overflow, Output. Digital Ground. Zener Reference Output. Three-State Output Enable Input, Active Low. See Table 1. ...
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... Full Scale - 1 LSB 6.20 4.96 Full Scale 6.30 5.04 Overflow 6.40 5.12 NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. CA3306, CA3306A, CA3306C TABLE 1. CHIP ENABLE TRUTH TABLE CE2 Valid 1 Three-State 0 Three-State TABLE 2. OUTPUT CODE TABLE ...
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... Also, an on-board zener is provided for use as a reference voltage. CA3306, CA3306A, CA3306C Continuous Clock Operation One complete conversion cycle can be traced through the CA3306 via the following steps. (Refer to timing diagram, Figure 1.) With the phase control in a “ ...
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... V 1 accomplish the adjustment. Set until the transition occurs. CA3306, CA3306A, CA3306C If V for the first transition is greater than the theoretical, IN then the 50 negative voltage of about 2 LSBs. The trim procedure is as stated previously. Gain Trim ...
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... A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. CA3306, CA3306A, CA3306C Signal-to-Noise (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the fi ...
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... Application Circuits V+ 1K CLOCK INPUT 0.1 F ADJUST POT 0.1 F FIGURE 17. TYPICAL CA3306 7-BIT RESOLUTION CONFIGURATION CA3306, CA3306A, CA3306C 0 CA3306 CE2 CE1 CLK DD VSS 0 REF REF CA3306 ...
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... Application Circuits (Continued) V+ CLOCK INPUT 0.1 F ADJUST POT 0.1 F FIGURE 18. TYPICAL CA3306 6-BIT RESOLUTION CONFIGURATION WITH DOUBLE SAMPLING RATE CAPABILITY CA3306, CA3306A, CA3306C 0.1 F CA3306 CE2 CE1 CLK DD VSS 0 ...
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... TYPICAL FOR: PHASE CE1 CE2 7406 OPEN COLLECTOR DRIVER CA3306 OUTPUTS TYPICAL FOR: CA3306 FIGURE 20. 5V LOGIC INTERFACE CIRCUIT FOR V CA3306, CA3306A, CA3306C B6’ NO. 1 6-BIT FLASH B1’ ADC 6-BIT DAC (12 BIT ACCURACY) X32 B6 NO. 2 6-BIT FLASH B1 ADC B7 NO ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 CA3306, CA3306A, CA3306C EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...