CA3304A Intersil Corporation, CA3304A Datasheet - Page 10

• Manufacturer Part Number: CA3304A
• Description: 4-Bit / 25 MSPS / Flash A/D Converters
• Manufacturer: Intersil Corporation

Offset Trim
In general offset correction can be done in the preamp
circuitry by introducing a DC shift to V
of the op amp. When this is not possible the V
be adjusted to produce an offset trim.
The theoretical input voltage to produce the first transition is
1
V
Adjust offset by applying this input voltage and adjusting the
V
alternating between 0 and 1 occurs.
Gain Trim
In general the gain trim can also be done in the preamp circuitry
by introducing a gain adjustment for the op amp. When this is
not possible, then a gain adjustment circuit should be made to
adjust the reference voltage. To perform this trim, V
set to the 15 to overflow transition. That voltage is
than V
To perform the gain trim, first do the offset trim and then
apply the required V
adjust V
Layout, Input And Supply Considerations
The CA3304 should be mounted on a ground-planed,
printed-circuit board, with good high-frequency decoupling
capacitors mounted as close as possible. If the supply is
noisy, decouple V
The CA3304 outputs current spikes to its input at the start of
the auto-balance and sample clock phases. A low
impedance source, such as a locally-terminated 50
cable, should be used to drive the input terminal. A fast-
settling buffer such as the HA-5033, HA-5242, or CA3450
should be used if the source is high impedance. The V
terminals also have current spikes, and should be well
bypassed.
Care should be taken to keep digital signals away from the
analog input, and to keep digital ground currents away from
the analog ground. If possible, the analog ground should be
connected to digital ground only at the CA3304.
Bipolar Operation
The CA3304, with separate analog (V
(V
operation. The V
supply (observing maximum voltage ratings to V
and recommended rating to V
potential also to be negative. Figure 12B shows operation
with an input range of -1V to +1V. Similarly, V
V
for an input range above the digital supply.
V
/
REF
REF
IN
2
lN
DD
LSB. The equation is as follows:
(0 to 1 transition) =
(15 to 16 transition) = V
, V
- voltage or input amplifier offset until an output code
+ could be maintained at a higher voltage than V
REF
REF
SS
+ and is calculated as follows:
) supply pins, allows true bipolar or negative input
+ until that transition occurs on the outputs.
AA
AA
+ with a resistor as shown in Figure 12A.
IN
- pin may be returned to a negative
= V
for the 15 to overflow transition. Now
1
= V
/
REF
2
LSB =
REF
REF
/32.
SS
- V
(31/32).
), thus allowing the V
1
/
REF
2
(V
IN
AA
REF
/32
or by the offset trim
+, V
/16)
AA
REF
-) and digital
1
IN
AA
CA3304, CA3304A
/
- input can
2
should be
+ or V
AA
LSB less
+ and
REF
coax
REF
DD
DD
-
4-16
,
Digital Input And Output Levels
The clock input is a CMOS inverter operating from and with
logic input levels determined by the V
V
necessary to level shift the clock input to meet the required
30% to 70% of V
ple for a negative V
An alternate way of driving the clock is to capacitively couple
the pin from a source of at least 1V
feedback resistor will keep the DC level at the intrinsic trip
point. Extremely non-symmetrical clock waveforms should
be avoided, however.
The remaining digital inputs and outputs are referenced to
V
drive the CA3304, either pull-up resistors or CD74HCT
series “QMOS” buffers are recommended.
5-Bit Resolution
To obtain 5-bit resolution, two CA3304s can be wired together.
Necessary ingredients include an open-ended ladder net-
work, an overflow indicator, three-state outputs, and chip-
enable controls - all of which are available on the CA3304.
The first step for connecting a 5-bit circuit is to totem-pole
the ladder networks, as illustrated in Figure 13. Since the
absolute-resistance value of each ladder may vary, external
trim of the mid-reference voltage may be required.
The overflow output of the lower device now becomes the
fifth bit. When it goes high, all counts must come from the
upper device. When it goes low, all counts must come from
the lower device. This is done simply by connecting the
lower overflow signal to the CE1 control of the lower A/D
converter and the CE2 control of the upper A/D converter.
The three-state outputs of the two devices (bits 1 through 4)
are now connected in parallel to complete the circuitry.
Definitions
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the CA3304. A low distortion sine
wave is applied to the input, it is sampled, and the output is
stored in RAM. The data is then transformed into the fre-
quency domain with a 4096 point FFT and analyzed to evalu-
ate the dynamic performance of the A/D. The sine wave input
to the part is -0.5dB down from full scale for all these tests.
Signal-to-Noise (SNR)
SNR is the measured RMS signal to RMS noise at a speci-
fied input and sampling frequency. The noise is the RMS
sum of all of the spectral components except the fundamen-
tal and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all other
spectral components below the Nyquist frequency excluding DC.
AA
DD
- are outside the range of the digital supplies, it may be
and V
SS
. If TTL or other lower voltage sources are to
AA
AA
input swing. Figure 12B shows an exam-
-.
AA
P-P
supplies. If V
. An internal 50k
AA
+ or