MT8967 Zarlink Semiconductor, Inc., MT8967 Datasheet - Page 7

• Manufacturer Part Number: MT8967
• Description: Integrated CODEC with A-Law companding and CCITT PCM encoding (20 pin PDIP-SOIC)
• Manufacturer: Zarlink Semiconductor, Inc.

Note: For Modes 1 and 2, F1i must be at logic low
for one period of 3.9 µs, in each 125 µs cycle, when
PCM data is being input and output, and the control
word at CSTi enters Register A. For Mode 3, F1i
must be at a logic low for two periods of 3.9 µs, in
each 125 µs cycle. In the first period, CA must be at
GNDD or V
high (V
Control Registers A, B
The contents of these registers control the filter/
codec functions as described in Tables 2 and 3.
Bit 7 of the registers is the MSB and is defined as the
first bit of the serial data stream input (corresponding
to the sign bit of the PCM word).
On initial power-up these registers are set to the
powerdown condition for a maximum of 25 clock
cycles. During this time it is impossible to change
the data in these registers.
Chip Testing
By enabling Register B with valid data (eight-bit
control word input to CSTi when F1i=GNDD and CA=
V
and 7 (most sign bits) define states for testing the
transmit filter, receive filter and the codec function.
The input in each case is V
each case is V
Loopback
Loopback of the filter/codec is controlled by the
control word entered into Register A. Bits 6 and 7
(most sign bits) provide either a digital or analog
loopback condition. Digital loopback is defined as
follows:
•
•
•
Analog loopback is defined as follows:
•
CC
) the chip testing mode can be entered. Bits 6
PCM input data at DSTi is latched into the PCM
input register and the output of this register is
connected to the input of the 3-state PCM
output register.
The digital input to the PCM digital-to-analog
decoder is disconnected, forced to zero (0).
The output of the PCM encoder is disabled and
thus the encoded data is lost. The PCM output
at DSTo is determined by the PCM input data.
PCM input data is latched, decoded and filtered
as normal but not output at V
DD)
.
EE
, and in the second period CA must be
R
output. (See Table 3 for details.)
X
input and the output in
R
.
ISO
2
-CMOS
MT8960/61/62/63/64/65/66/67
•
•
•
In both cases of
and DSTo is the output.
BIT 2
BIT 5
BIT 7
Analog output buffer at V
to GNDA and disconnected from the receive
filter output.
Analog input at V
transmit filter input.
The receive filter output is connected to the
transmit filter input. Thus the decode signal is
fed back through the receive path and encoded
in the normal way. The analog output buffer at
V
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
R
is not tested by this configuration.
Table 2. Control States - Register A
BIT 1
BIT 4
BIT 6
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
loopback,
X
BIT 0
BIT 3
is disconnected from the
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION CONTROL
Normal operation
Analog Loopback
Digital Loopback
R
Powerdown
has its input shorted
FILTER GAIN (dB)
FILTER GAIN (dB)
TRANSMIT (A/D)
RECEIVE (D/A)
DSTi is the input
+ 1
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
- 1
- 2
- 3
- 4
- 5
- 6
- 7
0
0
6-25